Keywords   Main page [CHM] Embedded Beans Bean Categories CPU beans Compilers

Keywords and corresponding Beans The keyword identifies a peripheral feature or functionality. There is a list of beans that support specified feature under each keyword. A/D converter - Analog-to-Digital Converter. A device that converts continuously varying analog signals into binary code. ADC - A/D converter Init_ADC - Peripheral Initialization Bean for the following CPU families: -HCS12X - Analog-to-Digital Converter (ADC) -HCS12 - Analog-to-Digital Converter (ADC) A/D resolution - Resolution of A/D Converter. ADC - A/D converter Acceptance filter - Define the acceptance patterns of the message frame identifier (ID). User aplication is notified about message reception only in case of acceptance filter hit. Byteflight - Byteflight communication interface FreescaleCAN - CAN communication for Freescale implementation ACK - Acknowledge. A transmission control character transmitted by the receiving station as an affirmative response to the sending station. FreescaleCAN - CAN communication for Freescale implementation InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. Address bus - Addresses are sent over the address bus to signal a memory location, to access on an external periphery, etc. Ext16IO - External 16-bit Input/Output Ext32IO - External 32-bit Input/Output Ext8IO - External 8-bit Input/Output ExtBitIO - External 1-bit Input/Output with Direction Register ExtByteIO - External Byte Input/Output (8 bits) with Direction Register Analog multiplexer - A device that selects one of possible analog inputs ADC - A/D converter Arbitration - If communication type allows two transmitters to start sending different messages on the bus simultaneously, arbitration procedure handles the message integrity. The transmitter, which loses arbitration, stop the transmission and usually reports this as an event. BDLC - BDLC serial communication FreescaleCAN - CAN communication for Freescale implementation InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. Asynchronous serial communication - Asynchronous serial communication transmits the data in a sequence (frame) as a series of bits with a given speed. The beginning and end of each frame must be identified by start and stop symbols. A precise clock (timing signal) is needed in the receiver to identify the boundaries between the bits, because no clock signal is send over communication intrface. Also SCI, UART. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) Baud rate - Baud rate is a measure of the number of times per second a signal in a communications channel changes state. The state is usually voltage level, frequency, or phase angle. If each baud causes the transmission of just one bit, so the baud rate is equal to the bit rate. However, for a channel that uses four bits per baud (e.g., CCITT V.22), the baud rate is 1/4 of the bit rate. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) BDLC - Byte data link controller is a peripheral that provides access to an external serial communication multiplex bus, operating according to the SAE J1850 protocol. BDLC - BDLC serial communication Init_BDLC - Peripheral Initialization Bean for the CPU family HCS12 - Society of Automotive Engineers (SAE) J1850 serial communication network. (BDLC) Bit rate - Bit rate (i.e. bits per second, abbreviated bps) is a measure of the number of data bits (digital 0s and 1s) transmitted each second in a digital communications channel. If each baud causes the transmission of just one bit, so the baud rate is equal to the bit rate. However, for a channel that uses four bits per baud (e.g., CCITT V.22), the baud rate is 1/4 of the bit rate. FreescaleCAN - CAN communication for Freescale implementation InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. Bit stuffing - The insertion of noninformation bits into data. If several successive bits (e.g. five) with the same level are transmitted on the bus, additional bit with opposite level is stuffed into the message. This procedure is used for error detection and receiver synchronization. FreescaleCAN - CAN communication for Freescale implementation Break symbol - The break symbol in SCI communication is recognized when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. The break symbol leads to report framing error. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave Bus clock - Frequency of the CPU internal bus. The internal bus clock is usually used CPU core and on-chip peripherals timing. FreeCntr - Free running counter Byteflight - The communication device that interfaces a MCU and the optical transceiver device Infineon (SPF BFT003) for receiving and transmitting messages according to BMW Byteflight specification. Byteflight - Byteflight communication interface Init_BYTEFLIGHT - Peripheral Initialization Bean for the CPU family HCS12 - Byteflight communication interface (BYTEFLIGHT) CAN - Controller Area Network is a serial communication protocol, originally defined by Bosh, targeted to the automotive industry. Link to detailed specification can be found web-site. FreescaleCAN - CAN communication for Freescale implementation Init_MSCAN - Peripheral Initialization Bean for the following CPU families: -HCS12X - Motorola Scalable Controller Area Network (MSCAN) -HCS12 - Motorola Scalable Controller Area Network (MSCAN) Capture - Capture register stores a copy of the counter's value when an input edge is detected. Capture - Timer capture encapsulation Init_ECT - Peripheral Initialization Bean for the following CPU families: -HCS12X - Enhanced Capture Timer (ECT) -HCS12 - Enhanced Capture Timer (ECT) Init_TIM - Peripheral Initialization Bean for the CPU family HCS12 - Timer Interface Module(TIM) Clock idle polarity - In SPI, clock idle polarity determines the logic state of the clock signal between transmissions. All SPI modules must have identical setting. SWSPI - Software synchronous serial communication SynchroMaster - Master for synchronous serial communication SynchroSlave - Slave for synchronous serial communication Clock signal - A reference source of timing information. A device providing signals used in a transmission system to control the timing of the duration of signal elements (bits) or the sampling rate. EventCntr8 - Event counter 8-bit FreeCntr - Free running counter InternalI2C - Internal I2C Communication Interface PWMMC - Pulse width modulation for motor control SW_I2C - SW emulated I2C using two I/O pins. SWSPI - Software synchronous serial communication SynchroMaster - Master for synchronous serial communication SynchroSlave - Slave for synchronous serial communication Communication - Information (data) transfer, among processors or peripherals, according to agreed conventions. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave BDLC - BDLC serial communication Byteflight - Byteflight communication interface FreescaleCAN - CAN communication for Freescale implementation FreescaleEMAC - Configuration modes for MC9S12NE64 EMAC start-up FreescaleEthernetAPI - NE64 ethernet API routines Init_BDLC - Peripheral Initialization Bean for the CPU family HCS12 - Society of Automotive Engineers (SAE) J1850 serial communication network. (BDLC) Init_BYTEFLIGHT - Peripheral Initialization Bean for the CPU family HCS12 - Byteflight communication interface (BYTEFLIGHT) Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) Init_SPI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Peripheral Interface (SPI) -HCS12 - Serial Peripheral Interface (SPI) InternalI2C - Internal I2C Communication Interface SWSPI - Software synchronous serial communication SynchroMaster - Master for synchronous serial communication SynchroSlave - Slave for synchronous serial communication Compare - Compare register contains value used for invoking some action (e.g. interrupt, toggle output pin, reset counter) FreeCntr - Free running counter FreeCntr16 - Free running 16-bit counter FreeCntr32 - Free running 32-bit counter FreeCntr8 - Free running 8-bit counter Init_ECT - Peripheral Initialization Bean for the following CPU families: -HCS12X - Enhanced Capture Timer (ECT) -HCS12 - Enhanced Capture Timer (ECT) Init_RTI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Real Time Interrupt(RTI) -HCS12 - Real Time Interrupt(RTI) Init_TIM - Peripheral Initialization Bean for the CPU family HCS12 - Timer Interface Module(TIM) PPG - Programmable pulse generation PWM - Pulse width modulation RTIshared - Real Time Interrupt Shareable TimeDate - Time and date TimerInt - Periodic interrupt TimerOut - Flip-flop output 1:1 Conversion time - Time of conversion that performs e.g. A/D Converter. ADC - A/D converter Counter - Basic part of the timer. Counter counts internal clock, external clock or events. Capture - Timer capture encapsulation EventCntr16 - Event counter 16-bit EventCntr32 - Event counter 32-bit EventCntr8 - Event counter 8-bit FreeCntr - Free running counter FreeCntr16 - Free running 16-bit counter FreeCntr32 - Free running 32-bit counter FreeCntr8 - Free running 8-bit counter Init_RTI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Real Time Interrupt(RTI) -HCS12 - Real Time Interrupt(RTI) Init_TIM - Peripheral Initialization Bean for the CPU family HCS12 - Timer Interface Module(TIM) PPG - Programmable pulse generation PulseAccumulator - Pulse Accumulator PWM - Pulse width modulation RTIshared - Real Time Interrupt Shareable TimeDate - Time and date TimerInt - Periodic interrupt TimerOut - Flip-flop output 1:1 CRC - Cyclic Redundancy Check. An error-detection scheme that uses parity bits generated by polynomial encoding of digital signals, appends those parity bits to the digital signal, and uses decoding algorithms that detect errors in the received digital signal. BDLC - BDLC serial communication Byteflight - Byteflight communication interface FreescaleCAN - CAN communication for Freescale implementation InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. D/A converter - Digital-to-Analog Converter. A device that converts digital pulses into analog signals. DAC - D/A converter PWMMC - Pulse width modulation for motor control Data bus - The data are transferred over the data bus, for example between CPU and an external peripheral. Ext16IO - External 16-bit Input/Output Ext32IO - External 32-bit Input/Output Ext8IO - External 8-bit Input/Output ExtBitIO - External 1-bit Input/Output with Direction Register ExtByteIO - External Byte Input/Output (8 bits) with Direction Register Data frame - Data frame is used to carry data over communication interface. FreescaleCAN - CAN communication for Freescale implementation Direction - Input or output can be the direction of the pin. BitIO - General 1-bit Input/Output BitsIO - General Multi-Bits Input/Output (1-8 bits) Byte2IO - General Two-Bytes Input/Output Byte3IO - General Three-Bytes Input/Output Byte4IO - General Four-Bytes Input/Output ByteIO - General Byte Input/Output (8 bits) ExtBitIO - External 1-bit Input/Output with Direction Register ExtByteIO - External Byte Input/Output (8 bits) with Direction Register WordIO - General Word (16-bit) Input/Output Dominant level - During simultaneous transmission of dominant and recessive bits, the resulting bus value will be dominant. In case of wired-AND implementation of the communication bus the dominant level would be logical 0 and recessive level logical 1. BDLC - BDLC serial communication Byteflight - Byteflight communication interface FreescaleCAN - CAN communication for Freescale implementation Duty - Ratio of PWM output signal. PPG - Programmable pulse generation PWM - Pulse width modulation Edge - Edge detector of timer enables set up condition of some event such as Capture, Generating of output pulse, reset counter etc. Capture - Timer capture encapsulation EventCntr16 - Event counter 16-bit EventCntr32 - Event counter 32-bit EventCntr8 - Event counter 8-bit PulseAccumulator - Pulse Accumulator EEPROM - Electrically Erasable Programmable Read-Only Memory. A non-volatile storage device using a technique similar to the floating gates in EPROMs but with the capability to discharge the floating gate electrically. Init_EEPROM - Peripheral Initialization Bean for the following CPU families: -HCS12X - EEPROM Memory (EEPROM) -HCS12 - EEPROM Memory (EEPROM) IntEEPROM - Internal EEPROM EOD - End Of Data. BDLC - BDLC serial communication EOF - End Of Frame. BDLC - BDLC serial communication FreescaleCAN - CAN communication for Freescale implementation Error active - In CAN communication, if the nodes in Error active state detect an error, they send active error flag on the bus. Active error flag consist of six successive dominant bits. FreescaleCAN - CAN communication for Freescale implementation Error frame - In CAN communication, Error frame is transmitted by any unit on detecting a bus error. FreescaleCAN - CAN communication for Freescale implementation Error pasive - In CAN communication, if the nodes in Error pasive state detect an error, they send pasive error flag on the bus. Pasive error flag consist of six successive recessive bits. FreescaleCAN - CAN communication for Freescale implementation Extended message frame - In CAN communication, Identifier of an Extended frame has 29 bits. In contrast identifier of a Standard frame has 11 bits. Extended message frame has recessive IDE bit. FreescaleCAN - CAN communication for Freescale implementation FIFO - A data structure or hardware buffer from which items are taken out in the same order they were put in. Byteflight - Byteflight communication interface Flash EPROM - Flash Erasable Programmable Read-Only Memory. A kind of non-volatile storage device similar to EEPROM, but where erasing can only be done in blocks or the entire chip. Init_FLASH - Peripheral Initialization Bean for the following CPU families: -HCS12X - Flash Memory (FLASH) -HCS12 - Flash Memory (FLASH) IntFLASH - Internal FLASH Frame - In data transmission, the sequence of contiguous bits delimited by, and including, beginning and ending flag sequences. A frame usually includes an information field, and usually consists of a specified number of bits between flags and contains an address field, a control field, a frame check sequence, flags and bits which may be used for error detection or control. Additional bits may be used for routing, synchronization, or overhead information not directly associated with the original data. BDLC - BDLC serial communication Byteflight - Byteflight communication interface FreescaleCAN - CAN communication for Freescale implementation Freerun - Counter mode when the counter starts from zero after reset, counting to maximal value, then wraps around. Capture - Timer capture encapsulation FreeCntr - Free running counter FreeCntr16 - Free running 16-bit counter FreeCntr32 - Free running 32-bit counter FreeCntr8 - Free running 8-bit counter RTIshared - Real Time Interrupt Shareable TimeDate - Time and date General call address - General call address is used for addressing every device connected to the I2C bus. InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. GPIO - General Purpose Input/Output. It's an one of possible pin features. BitIO - General 1-bit Input/Output BitsIO - General Multi-Bits Input/Output (1-8 bits) Byte2IO - General Two-Bytes Input/Output Byte3IO - General Three-Bytes Input/Output Byte4IO - General Four-Bytes Input/Output ByteIO - General Byte Input/Output (8 bits) ExtInt - External interrupt WordIO - General Word (16-bit) Input/Output Handshake - In data communications, a sequence of events governed by hardware or software, requiring mutual agreement of the state of the operational modes prior to information exchange. AsynchroSerial - Asynchronous serial communication Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) Character length - Number of data bits transmitted as one character. In SCI communication, 8. bits is the most common character length, but also 9. bits character length is often used. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) I2C - Inter-IC (Inter Integrated Circuit) bus. I2C bus, de facto standard developed by Phillips, is a bi-directional two-wire serial bus that provides a communication link between integrated circuits. Link to detailed specification can be found web-site. Init_IIC - Peripheral Initialization Bean for the following CPU families: -HCS12X - Inter-IC Bus (IIC) -HCS12 - Inter-IC Bus (IIC) InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. IDE - Identifier extended. In CAN frame, the IDE bit is recessive for Extended message frame and dominant for Standard message frame. I.e. Standard message frame has priority over Extended message frame. FreescaleCAN - CAN communication for Freescale implementation Idle symbol - The idle symbol in SCI communication contains all logic 1 and has no start, stop or parity bit. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave IFR - In-Frame Response. In SAE J1850 communication protocol, receiver of the frame sends immediate response that is considered to be in the same frame as sent message. BDLC - BDLC serial communication Interrupt vector - Interrupt vector points to a routine in memory, which handles the interrupt. InterruptVector - Interrupt vector handled in user code Interrupt - A signal that gets the attention of the CPU and may be generated for example by timer, external signal, at the end of ADC conversion, etc. ExtInt - External interrupt FreeCntr - Free running counter Init_API - Peripheral Initialization Bean for the CPU family HCS12X - Autonomous Periodic Interrupt (API) Init_RTI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Real Time Interrupt(RTI) -HCS12 - Real Time Interrupt(RTI) RTIshared - Real Time Interrupt Shareable TimeDate - Time and date TimerInt - Periodic interrupt Loopback mode - A communication peripheral may support internal loop back which can be used for self-test operation. The bit stream of the transmitter is fed back to the receiver internally. BDLC - BDLC serial communication FreescaleCAN - CAN communication for Freescale implementation Master - In computer networking, master/slave is a model for a communication protocol in which one device (known as the master) controls one or more other devices (known as slaves). AsynchroMaster - Asynchronous serial communication - master AsynchroSlave - Asynchronous serial communication - slave Byteflight - Byteflight communication interface InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. SWSPI - Software synchronous serial communication SynchroMaster - Master for synchronous serial communication SynchroSlave - Slave for synchronous serial communication Memory - These days, usually used synonymously with Random Access Memory or Read-Only Memory, but in the general sense it can be any device that can hold data in machine-readable format. Init_EEPROM - Peripheral Initialization Bean for the following CPU families: -HCS12X - EEPROM Memory (EEPROM) -HCS12 - EEPROM Memory (EEPROM) Init_FLASH - Peripheral Initialization Bean for the following CPU families: -HCS12X - Flash Memory (FLASH) -HCS12 - Flash Memory (FLASH) IntEEPROM - Internal EEPROM IntFLASH - Internal FLASH Modulation - The process, or result of the process, of varying a characteristic of a carrier, in accordance with an information-bearing signal. PWMMC - Pulse width modulation for motor control Multi-master - In computer networking, master/slave is a model for a communication protocol in which one device (known as the master) controls one or more other devices (known as slaves). Multi-master bus means that more than one device capable of controlling the bus can be connected to it. InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. Multiple channel Scan mode - A mode of A/D Converter in which the device samples across channels without SW intervention. ADC - A/D converter NACK - Negative acknowledge character (also NAK). A transmission control character transmitted by the receiving station as not affirmative response to the sending station. InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. Non-volatile memory - A term describing a storage device whose contents are preserved when its power is off. IntFLASH - Internal FLASH Normalisation bit - In SAE J1850 communication protocol user can choose if normalization bit log. 0 is transmitted, when response part of an in-frame response ends with CRC and log. 1 for in-frame response without CRC or vice versa. BDLC - BDLC serial communication NRZ - Non-Return-To-Zero. A code in which "1s" are represented by one significant condition and "0s" are represented by another, with no neutral or rest condition. E.g. SCI is NRZ format - 8 successive same logical bits are transmitted without returning of the signal to the idle state. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave Byteflight - Byteflight communication interface Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) Open drain - Open drain may be a feauture of pin output drivers. BitIO - General 1-bit Input/Output BitsIO - General Multi-Bits Input/Output (1-8 bits) Byte2IO - General Two-Bytes Input/Output Byte3IO - General Three-Bytes Input/Output Byte4IO - General Four-Bytes Input/Output ByteIO - General Byte Input/Output (8 bits) WordIO - General Word (16-bit) Input/Output Overflow - When counter gets over its maximal value and starts again from its defined minimal value (when counter counts down then counter underflow occurs when counter gets under its minimal value and starts counting down from its maximal value). Capture - Timer capture encapsulation EventCntr16 - Event counter 16-bit EventCntr32 - Event counter 32-bit EventCntr8 - Event counter 8-bit FreeCntr16 - Free running 16-bit counter FreeCntr32 - Free running 32-bit counter FreeCntr8 - Free running 8-bit counter Overload frame - In CAN communication, Overload frame is used to provide for an extra delay between the preceding and the succeeding Data or Remote frames. FreescaleCAN - CAN communication for Freescale implementation Overrun - A frequent consequence of data arriving faster than it can be consumed, especially in serial line communications. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave BDLC - BDLC serial communication Byteflight - Byteflight communication interface FreescaleCAN - CAN communication for Freescale implementation Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. SWSPI - Software synchronous serial communication SynchroMaster - Master for synchronous serial communication SynchroSlave - Slave for synchronous serial communication Parity - An error detection procedure in which a bit (0 or 1) added to each group of bits so that it will have either an odd number of 1's or an even number of 1's; e.g., if the parity is odd then any group of bits that arrives with an even number of 1's must contain an error. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) Period - Period of periodical event. FreeCntr - Free running counter Init_API - Peripheral Initialization Bean for the CPU family HCS12X - Autonomous Periodic Interrupt (API) Init_PIT - Peripheral Initialization Bean for the CPU family HCS12X - Periodic Interrupt Timer (PIT) Init_RTI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Real Time Interrupt(RTI) -HCS12 - Real Time Interrupt(RTI) PPG - Programmable pulse generation PWM - Pulse width modulation RTIshared - Real Time Interrupt Shareable TimeDate - Time and date TimerInt - Periodic interrupt TimerOut - Flip-flop output 1:1 WatchDog - WatchDog bean Pin - The pin is a connecting point on the package that is for connecting CPU into circuit. There are analog, digital, feeding, input/output etc. pins. BitIO - General 1-bit Input/Output BitsIO - General Multi-Bits Input/Output (1-8 bits) Capture - Timer capture encapsulation EventCntr16 - Event counter 16-bit EventCntr32 - Event counter 32-bit EventCntr8 - Event counter 8-bit ExtBitIO - External 1-bit Input/Output with Direction Register ExtInt - External interrupt InputPin - General 1-bit Input PPG - Programmable pulse generation PulseAccumulator - Pulse Accumulator PWM - Pulse width modulation TimerOut - Flip-flop output 1:1 Port - A group of pins, which have something in common, e.g. register set. BitsIO - General Multi-Bits Input/Output (1-8 bits) Byte2IO - General Two-Bytes Input/Output Byte3IO - General Three-Bytes Input/Output Byte4IO - General Four-Bytes Input/Output ByteIO - General Byte Input/Output (8 bits) ExtByteIO - External Byte Input/Output (8 bits) with Direction Register WordIO - General Word (16-bit) Input/Output PPG - Program Pulse Generator. Device can genarate pulses of variable period and duty. Init_PMF - Peripheral Initialization Bean for the CPU family HCS12 - Pulse width Modulator with Fault protection (PMF) Init_PWM - Peripheral Initialization Bean for the following CPU families: -HCS12X - Pulse Width Modulator (PWM) -HCS12 - Pulse Width Modulator (PWM) PPG - Programmable pulse generation Pull resistor - Pin property, where it's possible to connect through resistor a pin with Vcc (pull up) or GND (pull down) internally. BitIO - General 1-bit Input/Output BitsIO - General Multi-Bits Input/Output (1-8 bits) Byte2IO - General Two-Bytes Input/Output Byte3IO - General Three-Bytes Input/Output Byte4IO - General Four-Bytes Input/Output ByteIO - General Byte Input/Output (8 bits) WordIO - General Word (16-bit) Input/Output PWM - Pulse Width Modulation. Device can generate pulses of variable duty. Init_PMF - Peripheral Initialization Bean for the CPU family HCS12 - Pulse width Modulator with Fault protection (PMF) Init_PWM - Peripheral Initialization Bean for the following CPU families: -HCS12X - Pulse Width Modulator (PWM) -HCS12 - Pulse Width Modulator (PWM) PWM - Pulse width modulation PWMMC - Pulse width modulation for motor control Raw data - Regarding pins, this signalize possibility of reading real levels on pins. It doesn't depend on mode of pins. BitIO - General 1-bit Input/Output BitsIO - General Multi-Bits Input/Output (1-8 bits) Byte2IO - General Two-Bytes Input/Output Byte3IO - General Three-Bytes Input/Output Byte4IO - General Four-Bytes Input/Output ByteIO - General Byte Input/Output (8 bits) InputPin - General 1-bit Input WordIO - General Word (16-bit) Input/Output Recesive level - During simultaneous transmission of dominant and recessive bits, the resulting bus value will be dominant. In case of wired-AND implementation of the communication bus the dominant level would be logical 0 and recessive level logical 1. BDLC - BDLC serial communication Byteflight - Byteflight communication interface FreescaleCAN - CAN communication for Freescale implementation Reduced drive - Reduced drive property enables reducing current through the pin in output mode. BitIO - General 1-bit Input/Output BitsIO - General Multi-Bits Input/Output (1-8 bits) Byte2IO - General Two-Bytes Input/Output Byte3IO - General Three-Bytes Input/Output Byte4IO - General Four-Bytes Input/Output ByteIO - General Byte Input/Output (8 bits) WordIO - General Word (16-bit) Input/Output Reload - Content of reload register is written into the counter from its initialization value. FreeCntr - Free running counter FreeCntr16 - Free running 16-bit counter FreeCntr32 - Free running 32-bit counter FreeCntr8 - Free running 8-bit counter Init_RTI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Real Time Interrupt(RTI) -HCS12 - Real Time Interrupt(RTI) PPG - Programmable pulse generation PWM - Pulse width modulation PWMMC - Pulse width modulation for motor control RTIshared - Real Time Interrupt Shareable TimeDate - Time and date TimerInt - Periodic interrupt TimerOut - Flip-flop output 1:1 Remote frame - In CAN communication, a remote frame is transmitted by a bus unit to request the transmission of the Data frame with the same identifier. Remote frame has recessive RTR bit and Data frame has dominant RTR bit. FreescaleCAN - CAN communication for Freescale implementation Repeated start condition - In I2C bus a repeated start condition is used to generate Start condition without first generating a Stop condition to terminate the communication. This is used by master to communicate with another slave or with the same slave in a different mode without releasing the bus. InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. WatchDog - WatchDog bean RS232 - RS-232 is a standard for an electrical interface between Data Terminal Equipment (DTE) and Data Circuit-Terminating Equipment (DCE) such as modems. It appears also in diferent names such as RS-232C, RS-232D, EIA232, V.24, V.28 or V.10 but essentially all these interfaces are interoperable. RS-232 is used for asynchronous serial data transfer as well as synchronous links such as SDLC, HDLC, Frame Relay and X.25 Link to detailed specification can be found web-site. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) RTC - Real time clock. Device contains actual time and date and usually alarm registers too. TimeDate - Time and date RTR - Remote transmission request bit. In CAN frame RTR bit is dominant in Data frame and recessive in Remote frame (reques for data). I.e. the Data frame has priority over Remote frame. FreescaleCAN - CAN communication for Freescale implementation RxD - A label of the pin used as receive input of the asynchronous serial communication device. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) SAE J1850 - Society of automotive engineers J1850 standard is a standard of serial communication network and protocol in automotive industry. It implements serial communication over one wire. BDLC - BDLC serial communication Init_BDLC - Peripheral Initialization Bean for the CPU family HCS12 - Society of Automotive Engineers (SAE) J1850 serial communication network. (BDLC) SCI - Serial communication interface. Interface to the asynchronous serial communication (UART). AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) SCL - A label of the pin used as clock input/output of the I2C communication device. InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. SDA - A label of the pin used as data input/output of the I2C communication device. InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. Sequential measurement - A/D Converter at once measures always one channel only. ADC - A/D converter Shift clock edge - In SPI communication determines whether data are shifted on rising or falling edge of the clock signal. All SPI modules must have identical setting. SWSPI - Software synchronous serial communication SynchroMaster - Master for synchronous serial communication SynchroSlave - Slave for synchronous serial communication Simultaneous measurement - Ability of some A/D converters to measure 2 channels at once. ADC - A/D converter Slave select - Slave select (or SS) is label of the pin used in SPI communication device for selecting a slave device. SynchroMaster - Master for synchronous serial communication SynchroSlave - Slave for synchronous serial communication Slave - In computer networking, master/slave is a model for a communication protocol in which one device (known as the master) controls one or more other devices (known as slaves). AsynchroMaster - Asynchronous serial communication - master AsynchroSlave - Asynchronous serial communication - slave Byteflight - Byteflight communication interface InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. SWSPI - Software synchronous serial communication SynchroMaster - Master for synchronous serial communication SynchroSlave - Slave for synchronous serial communication SOF - Start of frame. BDLC - BDLC serial communication FreescaleCAN - CAN communication for Freescale implementation SPI - Serial Peripheral Interface. SPI is a serial protocol in which clocking information is transmitted along with the data signal. Typically the master device creates the clock and the slave device uses the master's clock to shift data into or out of itself. This means that the SPI serial channel needs a minimum of two lines. The primary two lines are sometimes referred to as the data and clock lines. Also Synchronous serial communication. Link to detailed specification can be found web-site. Init_SPI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Peripheral Interface (SPI) -HCS12 - Serial Peripheral Interface (SPI) SWSPI - Software synchronous serial communication SynchroMaster - Master for synchronous serial communication SynchroSlave - Slave for synchronous serial communication Standard message frame - In CAN communication, identifier of a Standard frame has 11 bits. In contrast identifier of an Extended frame has 29 bits. Standard message frame has dominant IDE bit. FreescaleCAN - CAN communication for Freescale implementation Start bit - A bit which signals the start of transmission of a character on a serial line. In Asynchronous serial communication (SCI) it is logic 0. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave Byteflight - Byteflight communication interface Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) Start condition - In I2C bus a Start condition is generated by the master at the beginning of a transmission. After Start condition the bus is considered to be busy. InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. Stop bit - In serial communications, where each bit of the message is transmitted in sequence, stop bits are extra "1" bits which follow the data and any parity bit. They mark the end of a unit of transmission. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave Byteflight - Byteflight communication interface Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) Stop condition - In I2C bus a Stop condition is generated by the master at the end of a transmission. After Stop condition the bus is considered to be free. InternalI2C - Internal I2C Communication Interface SW_I2C - SW emulated I2C using two I/O pins. Synchronous serial communication - Synchronous serial communication transmits the data in a sequence as a series of bits and synchronization signal (clock) as a separate signal. Single bits are separated by means of the synchronization signal (clock) at receiver side. Also SCI. Init_SPI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Peripheral Interface (SPI) -HCS12 - Serial Peripheral Interface (SPI) SWSPI - Software synchronous serial communication SynchroMaster - Master for synchronous serial communication SynchroSlave - Slave for synchronous serial communication Timer - Common name for device made from counter, prescaler, comparator (reload register), capture, flip-flop, edge detector, generator of interrupts etc. It is used for generating periodical and/or nonperiodical events, shapes of signals, for time controlling of a process.\n Also this term is used just for the standalone counter. Capture - Timer capture encapsulation EventCntr16 - Event counter 16-bit EventCntr32 - Event counter 32-bit EventCntr8 - Event counter 8-bit FreeCntr - Free running counter FreeCntr16 - Free running 16-bit counter FreeCntr32 - Free running 32-bit counter FreeCntr8 - Free running 8-bit counter Init_API - Peripheral Initialization Bean for the CPU family HCS12X - Autonomous Periodic Interrupt (API) Init_ECT - Peripheral Initialization Bean for the following CPU families: -HCS12X - Enhanced Capture Timer (ECT) -HCS12 - Enhanced Capture Timer (ECT) Init_PIT - Peripheral Initialization Bean for the CPU family HCS12X - Periodic Interrupt Timer (PIT) Init_RTI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Real Time Interrupt(RTI) -HCS12 - Real Time Interrupt(RTI) Init_TIM - Peripheral Initialization Bean for the CPU family HCS12 - Timer Interface Module(TIM) PPG - Programmable pulse generation PulseAccumulator - Pulse Accumulator PWM - Pulse width modulation PWMMC - Pulse width modulation for motor control RTIshared - Real Time Interrupt Shareable TimeDate - Time and date TimerInt - Periodic interrupt TimerOut - Flip-flop output 1:1 Trigger mode - It is mode of A/D Converter, where it's enabled to run measurement by external (out of pin) or internal (for example out of timer) signal. ADC - A/D converter TxD - A label of the pin used as transmission output of the asynchronous serial communication device. AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) UART - Universal Asynchronous Receiver/Transmitter. An integrated circuit or peripheral used for serial asynchronous communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. Also Asynchronous serial communication or SCI AsynchroMaster - Asynchronous serial communication - master AsynchroSerial - Asynchronous serial communication AsynchroSlave - Asynchronous serial communication - slave Init_SCI - Peripheral Initialization Bean for the following CPU families: -HCS12X - Serial Communications Interface (SCI) -HCS12 - Serial Communications Interface (SCI) Processor ExpertTM and Embedded BeansTM are registered trademarks of UNIS, Ltd. ©1997-2005, UNIS, Ltd.