This bean emulates an I2C communication interface, which is based on the Philips I2C-bus specification version 2.0. The interface uses two general-purpose I/O pins, first for the Serial Data line (SDA), second for the Serial Clock line (SCL). Clock pulses of SCL are generated by software and no other hardware device is used by this bean.

Operating modes features:

MASTER

• Single master communication only (no other master is allowed on the bus)
• The combined format of communication possible (see Automatic stop condition property)
• 7-bit slave addressing (10-bit addressing can be made as well)
• No wait state initiated when a slave device holds the SCL line low
• No bus error detection provided

SLAVE - this operating mode is not implemented yet

• 7-bit slave addressing
• General call address detection not provided
• The combined format of communication not provided
• The stop condition detection not provided

This bean belongs to the category: CPU External Devices-Communication