Peripheral Beans cover all the hardware functionality and they are intended for expert use of the respective
peripherals. This bean implements the peripheral initialization of an internal J1850 serial communication network
- BDLC (BDLC) module of the Freescale HCS12 MCU derivatives.
Peripheral initialization
The bean contains no high level methods or events, it provides only initialization of the hardware module. By default is the internal
initialization called automatically from the "PE_low_level_init" in CPU module, analogous to the initialization of other
PE beans. However the calling of this init code in the CPU module can be disabled and the user may call this function in
another module.
If the initialization property
"Call init in CPU init.code" is set to
"no" then the initialization is removed
from the CPU module code and the user have to call the
'BeanName_Init()' function elsewhere, i.e. in the main module.
Interrupt service
Processor Expert™ generates interrupt service support of BDLC peripheral only for the interrupt vector which the ISR routine
name is specified for. Otherwise the interrupts are served by the default routine(s). The support include interrupt vector
hooking and priority setting for the respective interrupt vector.
The peripheral beans does not generate code for the interrupt service routines specified in the Interrupts properties group
of the Init_BDLC bean (see Bean Inspector window). If there are any of the interrupts enabled in the bean the user is responsible
for the handling of such ISR's. Correct interrupt service routine "ISR name" must be implemented in the user code.
Warning:
This is low level bean. Usually it is not possible to use one setting of this bean for different microcontrollers.
BDLC module
The BDLC module is a serial communication module which allows the user to send and receive messages
across a Society of Automotive Engineers (SAE) J1850 serial communication network. The user’s
software handles each transmitted or received message on a byte-by-byte basis, while the BDLC performs
all of the network access, arbitration, message framing and error detection duties.
It is recommended that the reader be familiar with the operation and requirements of the SAE J1850
protocol as described in the document “SAE Standard J1850 Class B Data Communications Network
Interface” prior to proceeding with this specification.
The BDLC module is designed in a modular structure for use as an IP block. A general working knowledge
of the IP Bus signals and bus control is assumed in the writing of this document. For details, refer to the
SRS IP Bus specifications.
Features of the BDLC module include the following:
- SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible for
Low-Speed (£ 125 Kbps) Serial Data Communications in Automotive Applications
- 10.4 Kbps Variable Pulse Width (VPW) Bit Format
- Digital Noise Filter
- Digital Loopback Mode
- 4X Receive Mode, 41.6 Kbps, Supported
- Block Mode Receive and Transmit Supported
- Collision Detection
- Hardware Cyclical Redundancy Check (CRC) Generation and Checking
- Dedicated Register for Symbol Timing Adjustments
- IP Bus Interface
- In-Frame Response (IFR) Types 0, 1, 2, and 3 Supported
- Power-Saving Stop and Wait Modes with Automatic Wakeup on Network Activity
- Polling and CPU Interrupt Generation with Vector Lookup Available
Peripheral Initialization Beans provide a low-level hardware approach to
initialize registers of the peripheral module. They are intended for experienced users.
This bean belongs to the category: CPU Internal Peripherals-Peripheral Initialization Beans
