Bean name - Name of the bean.
Device - Selection of the BDLC communication device module.
Settings - Common BDLC module settings.
• Clock settings - Clock/timing settings of the module.
  • Clock - The nominal BDLC operating frequency (mux interface clock frequency - fbdlc) must always be 1.048576 MHz or 1 MHz in order for J1850 bus communications to take place properly.
    This item modifies the CLKS bit in the DLCBCR1 register .
  • Prescaler - This item determines the amount by which the frequency of the system clock signal is divided to generate the MUX Interface clock (fbdlc) which defines the basic timing resolution of the MUX Interface. The value programmed into these bits is dependent on the chosen system clock frequency.
    This item modifies R0 bit up to R5 bit in the DLCBRSR register .
  • Frequency - Frequency information. This item is influenced by the following properties:Prescaler, Clock.
• State Machine Reset - The programmer can use this item to reset the BDLC state machines to an initial state after the user put the off-chip analog transceiver in loop back mode.
  This item modifies the SMRST bit in the DLCBCR2 register .
• Digital Loopback Mode - This item determines the source to which the input of the digital filter is connected and can be used to isolate bus fault conditions.
  This item modifies the DLOOP bit in the DLCBCR2 register .
• Receive 4X - This item determines if the BDLC operates at normal transmit and receive speed (10.4 kbps) or receive only at 41.6 kbps.
  This item modifies the RX4XE bit in the DLCBCR2 register .
• Normalization Bit Format - This item controls the format of the Normalization Bit (NB). SAE J1850 strongly encourages the use of an active long: ‘0’ for In-Frame Responses containing CRC and active short, ‘1’ for In-Frame Responses without CRC.
  This item modifies the NBFS bit in the DLCBCR2 register .
• Transmit In-Frame Response Control - This item controls the type of In-Frame Response being sent.
  This item modifies TSIFR, TMIFR0 and TMIFR1 bits in the DLCBCR2 register .
• Receive Pin Polarity - The Receive pin Polarity bit is used to select the polarity of incoming signal on the receive pin.Some external analog transceiver inverts the receive signal from the J1850 bus before feeding back to the digital receive pin.
  This item modifies the RXPOL bit in the DLCBARD register .
• BDLC transceiver Delay - This item adjusts the transmitted symbol timings to account for the differing roundtrip delays found in different SAE J1850 analog transceivers.The allowable delay range is from 9 ms to 24 ms, with a nominal target of 16 ms (reset value).
  This item modifies BO0 up to BO3 bits in the DLCBARD register .
• Stop in Wait Mode - Stop in Wait Mode.
  This item modifies the WCM bit in the DLCBCR1 register .
Pins - Module pins/signals settings.
• Transmit Pin - Transmit Pin.
• Transmit Pin signal - Signal name of Transmit Pin.
• Receive Pin - Receive Pin.
• Receive Pin signal - Signal name of Receive Pin.
Interrupts - Interrupts settings of the module.
• BDLC interrupt - BDLC interrupt settings.
  • BDLC interrupt - BDLC Interrupt enable.
    This item modifies the IE bit in the DLCBCR1 register .
  • Interrupt - Interrupt vector (for information only).
  • Priority - Priority of BDLC interrupt.
  • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
    Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the bean module header file.
Initialization - Initialization options of the module.
• Call Init in CPU init. code - The Init method of the bean may be called after power-on or reset (in initialization code) by PE.
  yes - The Init method is called by PE.
  no - The Init method is not called by PE, it should be called in user's code.
• BDLC module - BDLC module enable.
  This item modifies the BDLCE bit in the DLCSCR register .