• Bean name - Name of the bean.
• Device - Selection of the Timer device module.
• Settings - Common TIM module settings.
  • Clock settings - Clock/timing settings of the module.
    • Prescaler - Prescaler.
      This item modifies PR0, PR1 and PR2 bits in TSCR2 register.
      
      There are 8 options:
      
      • Bus Clock / 1: Prescale Factor
      • Bus Clock / 2: Prescale Factor
      • Bus Clock / 4: Prescale Factor
      • Bus Clock / 8: Prescale Factor
      • Bus Clock / 16: Prescale Factor
      • Bus Clock / 32: Prescale Factor
      • Bus Clock / 64: Prescale Factor
      • Bus Clock / 128: Prescale Factor
      
      
    • Frequency - Frequency. This item is influenced by the following properties: Prescaler.
    • Clock - Timer clock source selection.
      This item modifies CLK0, CLK1 bits in the PACTL register.
      
      There are 4 options:
      
      • Timer prescaler: Use timer prescaler clock as timer counter clock
      • PACLK: Use PACLK as input to timer counter clock
      • PACLK/256: Use PACLK/256 as timer counter clock frequency.
      • PACLK/65536: Use PACLK/65536 as timer counter clock frequency.
      
      
  • Fast Flag Clear - For TFLG1, a read from an input capture or a write to the output compare channel causes the corresponding channel flag, CnF, to be cleared. For TFLG2, any access to the TCNT register clears the TOF flag. Any access to the PACNT registers clears the PAOVF and PAIF flags in the PAFLG register. This has the advantage of eliminating software overhead in a separate clear sequence.
    This item modifies TFFCA bit in TSCR1 register.
  • Counter Reset Enable - This bit allows the timer counter to be reset by a successful output compare 7 event. This mode of operation is similar to an up-counting modulus counter.
    This item modifies TCRE bit in TSCR2 register.
  • List of Channels - List of Channels.
    One item of the list looks like:
    Channel - Channel group.
    • Capture Device - Capture Device.
    • Mode - Input Capture or Output Compare Channel Configuration.
      This item modifies IOSx bit in TIOS register.
      There are 2 modes:
      • Capture - The corresponding channel acts as an input capture The following items are displayed in this mode:
        • Input control - This item configures the input capture edge detector circuits.
          This item modifies EDGxA and EDGxB bit in TCTL4 register.
      • Compare - The corresponding channel acts as an output compare. The following items are displayed in this mode:
        • Compare Mask - Setting the OC7Mx will set the corresponding port to be an output port when the corresponding TIOSx bit is set to be an output compare.
          This item modifies OC7Mx bit in OC7M register.
        • Compare Data - A channel x output compare can cause bits in the output compare x data register to transfer to the timerport data register depending on the output compare x mask register.
          This item modifies OC7Dx bit in OC7D register.
          
          There are 2 options:
          
          • 0: This value will be transfered to output channel.
          • 1: This value will be transfered to output channel.
          
          
        • Toggle On Overflow - It toggles output compare pin on overflow.
          This item modifies TOVx bit in TTOV register.
        • Output action - This item specifies the output action to be taken as a result of a successful OCx compare.
          This item modifies OMx and OLx bit in TCTL2 register.
          
          There are 4 options:
          
          • Disconected: Timer disconnected from output pin logic.
          • Toggle output line: Toggle OCx output line.
          • Clear line to zero: Clear OCx output line to zero.
          • Set line to one: Set OCx output line to one.
          
          
        • Capture/Compare Register - Capture/Compare Register.
          This item modifies all bits in TCx register.
    • Channel interrupt - Channel interrupt settings
      • Channel interrupt - Enable/disable Input Capture/Output Compare Interrupt.
        This item modifies C0I to C7I bits in the TIE register.
      • Interrupt - Input Capture/Output Compare Interrupt.
      • Priority - Priority of channel.
      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
    • Pins - Channel pins/signals settings.
      • Channel pin - Channel pin.
      • Channel pin name - Channel pin name.
  • Pulse Accumulator - This group covers all settings for accumulator.
    • Accumulator counter - Accumulator counter device selection.
    • Accumulator - Accumulator device selection.
    • Pulse accumulator Mode - Pulse accumulator mode.
      This item modifies the PAMOD bit in the PACTL register.
      There are 2 modes:
      • Gated time accumulation - This bit is active only when the Pulse Accumulator A is enabled. The following items are displayed in this mode:
        • Edge Control - Pulse Accumulator Edge Control.
          This item modifies the PEDGE bit in the PACTL register.
          
          There are 2 options:
          
          • Div. by 64 clock enabled with pin low level: PT7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on PT7 sets the PAIF flag.
          • Div. by 64 clock enabled with pin high level: PT7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on PT7 sets the PAIF flag
          
          
      • Event counter - This bit is active only when the Pulse Accumulator A is enabled. The following items are displayed in this mode:
        • Edge Control - Pulse Accumulator Edge Control.
          This item modifies the PEDGE bit in the PACTL register.
          
          There are 2 options:
          
          • On rising edges: Rising edges on PT7 pin cause the count to be incremented.
          • On falling edges: Falling edges on PT7 pin cause the count to be incremented.
          
          
    • Accumulators Count Register - Accumulators Count Register.
      This item modifies all bits in the PACNT register.
    • Input pin - Input pin.
    • Input pin signal - Input pin signal name.
• Interrupts - Interrupts settings of the module.
  • Timer overflow - Timer overflow settings.
    • Timer overflow - Enable/disable Timer overflow interrupt.
      This item modifies the TOI bit in the TSCR2 register.
    • Interrupt - Interrupt vector (for information only).
    • Priority - Priority of timer overflow interrupt.
    • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
      Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the bean module header file.
  • Accumulator Overflow - Accumulator Overflow settings.
    • Accumulator Overflow - Enable/disable Accumulator overflow interrupt.
      This item modifies the PAOVI bit in the PACTL register.
    • Interrupt - Interrupt vector (for information only).
    • Priority - Priority of accumulator overflow interrupt.
    • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
      Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the bean module header file.
  • Accumulator Input - Accumulator Input settings.
    • Accumulator Input - Enable/disable Accumulator input interrupt.
      This item modifies the PAI bit in the PACTL register.
    • Interrupt - Interrupt vector (for information only).
    • Priority - Priority of accumulator input interrupt.
    • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
      Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the bean module header file.
• Initialization - Initialization options of the module.
  • Call Init in CPU init. code - The Init method of the bean may be called after power-on or reset (in initialization code) by PE.
    yes - The Init method is called by PE.
    no - The Init method is not called by PE, it should be called in user's code.
  • Timer - Timer enable.
    This item modifies the TEN bit in the TSCR1 register.
  • Pulse Accumulator - Accumulator enable.
    This item modifies the PAEN bit in the PACTL register.