MC9S12XDP512_144 Properties CPU Bean documentation

Bean name - Name of the bean
CPU type - Cpu variant
Shared clock settings - XDP512 - Clock settings group defined in separate file and shared among CPU beans.
One item of the list looks like:
Clock settings - MCU clock settings
- Input clock - This property includes settings of the input clock signals.
  - Oscillator frequency [MHz] - Frequency of the main crystal or external clock. The crystal oscillator range is 4-16 MHz (loop controlled Pierce) and 5-40 MHz (full swing Pierce), the external clock range is 0.5-80 MHz.
  - Clock input pin - Clock input properties.
    - Pin - Clock input pin name (for information only).
    - Pin signal - Clock input signal name.
  - Clock output pin - Clock output properties.
    - Pin - Clock output pin name (for information only).
    - Pin signal - Clock output signal name.
- Output clock - This property includes the output clock signals settings.
  - External clock - This property controls the availability of the free-running clock on the ECLK pin. The clock output is always active in emulation modes and if it is enabled, in all other operating modes as well.
    - ECLK pin - External clock output pin (for information only).
    - ECLK pin signal - Signal name of ECLK pin.
    - ECLK clock rate - These bits determine the rate of the free-running clock on the ECLK pin. The divider is always disabled in emulation modes and it is active as it is programmed in all other operating modes.
  - Fixed external clock - This property controls the availability of the free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the internal bus clock. The clock output is always active in emulation modes and in all other operating modes if it is enabled.
    - ECLKX2 pin - Fixed external clock output pin (for information only).
    - ECLKX2 pin signal - Signal name of ECLKX2 pin.
- Low-power modes settings - This group controls the CRG module clock selection.
  - Pseudo Stop - This property controls the functionality of the oscillator when the Stop Mode is active.
    If this property is set to 'yes', the oscillator continues to run in the Stop Mode (Pseudo Stop). The oscillator amplitude is reduced.
    If this property is set to 'no', the oscillator is disabled in the Stop Mode.
  - Fast wake-up from full stop - This property enables/disables fast wake-up from full stop mode.
  - PLL stops in wait mode - This property determines a behavior of the PLL module in the Wait Mode
    If this property is set to 'yes', the PLL module will operate in the Wait Mode.
    If this property is set to 'no', the PLL module will keep running in the Wait Mode.
  - RTI stops in Wait Mode - This property determines the behavior of the RTI in the Wait Mode.
    If this property is set to 'yes', the RTI module is stopped and it initializes the RTI dividers whenever the part goes into the Wait Mode.
    If this property is set to 'no', the RTI module keeps running in the Wait Mode.
  - COP stops in Wait Mode - This property determines a behavior of the COP module in the Wait Mode
    If this property is set to 'yes', the COP module is stopped and initializes the COP module dividers whenever the part goes into Wait Mode.
    If this property is set to 'no', the COP module keeps running in the Wait Mode.
- Clock monitor - This property specifies the behavior of Clock monitor.
Shared interrupts settings - XDP512 - Interrupts group defined in separate file and shared among CPU beans.
One item of the list looks like:
Interrupts initialization - Initial interrupt settings (CCR register)
- I-maskable interrupts - This property enables/disables the I-maskable interrupts after Processor Expert initialization (I-bit of CCRL register).
- Initialization priority - Initialization value of the I-maskable interrupt priority. This value is written to the IPL bits (CCRH) of the Condition Code Register (CCR).
  
  There are 9 options:
  - Dont initialize: No code for setting if IPL bits of CCR register will be generated.
  - 0:
  - 1:
  - 2:
  - 3:
  - 4:
  - 5:
  - 6:
  - 7:
Shared internal resource mapping - XDP512 - Internal resource mapping group defined in separate file and shared among CPU beans.
One item of the list looks like:
Internal resource mapping - Internal resource mapping setting
- Direct page mapping - This property determines the position of the direct page within the memory map. This vale is used by the CPU when performing accesses using the direct addressing mode. The value forms the bits [15:8] of the address.
- Interrupt/Reset vector table - This group contains the vector table placement settings.
  - Reset vectors - This group contains settings for placement of reset vectors.
    - Address - Address of the reset vectors part of the interrupt vectors table (IVT). Reset vector part of IVT will be placed on this address. The value doesn't affect any HW resources and it is intended for a bootloader or monitor support. This value only affects the address of the reset vectors part of the interrupt vector table in the Vectors.c file.
    - Size - Size of the reset vectors part of the interrupt vector table. (For information only)
  - Interrupt vectors - This group contains settings for placement of interrupt vectors.
    - Address - Address of the interrupt vector table (IVT). IVT will be placed on this address. This value affect IVBR register, but setting of this register can be suppressed (If the property 'Init IVBR reg.' is set to 'no' ) for bootloader or monitor support.
      This value also affects the address of the interrupt vector table in the Vectors.c file.
    - Size - Size of the interrupt vector table. (For information only)
    - Init. IVBR reg. - Initialization of IVBR(Interrupt Vector Base Register) register can be suppressed by setting this property to 'no' value. This feature can be useful for bootloader or monitor support. If enabled, IVBR is initialized with high byte value of interrupt vector table address. Note: Low byte of interrupt vector table should be set to 0x10.
Shared external bus and user mode - XDP512 - Shared external bus and user mode group defined in separate file and shared among CPU beans.
One item of the list looks like:
External bus and user mode - CPU operating mode and external bus settings.
- Boot operating mode - Set this property according to the CPU operating mode that is set during the reset (respectively before execution of an application). This MCU mode is set by the MODA:MODB:MODC pins during the reset (respectively set by debugger).
  Note:
  Processor Expert needs to known the operating mode to allocate IO pins required for selected mode and to make some settings available.
- Operation mode switching - This property enables to generate an operating mode switching code, i.e. it enables changing of the boot operating mode by application code. This operating mode is set by the 'Target operation mode' property (visible only if this property is set to 'yes')
  Set this property to 'yes' to generate code for switching of operating mode in the _EntryPoint() method.
  Note:
  Sometimes it is required to boot into some operation mode and switch to another mode by writing to the MODE register. This property allows user to switch from the boot operating mode into the selected operation mode. This switching is done in the CPU _EntryPoint() function.
  If the code for switching of operating mode is undesirable, be aware that most debugging tools provide the ability to self configure the device in the debugging environment (if the part is booted into special signal-chip mode). If the CPU is to be configured for expanded operation in secure mode, the CPU must exit reset in the expanded mode. No writes to the MOD bits are allowed while operating in the secure mode. However, to release security, special single-chip mode must be possible.
  For more information see the Application note AN2287
  - Target operation mode - Set this property according to the required MCU operating mode that will be set by the application code in the _EntryPoint() method.
- Operating mode settings - This group contains settings of external bus provided by the current operation mode. Operating mode is defined by the values of the MODA:MODB:MODC pins (property 'Boot operating mode') during reset and can be changed by writing to the MODE register (by using the property 'Target operation mode', if the property 'Operation mode switching' is set to 'yes')
  There are 6 modes:
  - Special single-chip - The following items are displayed in this mode:
    - Internal FLASH - This group contains settings of external bus provided by the current operation mode. Operating mode is defined by the values of the MODA:MODB:MODC pins (property 'Boot operating mode') during reset and can be changed by writing to the MODE register (by using the property 'Target operation mode', if the property 'Operation mode switching' is set to 'yes')
      - Int. FLASH in 0x4000-0x7FFF - If this property is "yes" then the fixed page of Flash or ROM can be accessed in the lower half of the memory map. Accesses to
        $4000–$7FFF(Page 0xFD) will be mapped to $7F_4000-$7F_7FFF in the global memory space.
    - Exernal bus - This property includes settings of the external bus.
      - Reduced Input Threshold - This property selects reduced input threshold on external data bus pins and specific control input signals which are in use with the external bus interface in order to adapt to external devices with a 3.3 V, 5 V tolerant I/O. If set to 'Enabled' the reduced input threshold level is enabled on pins in use with the external bus interface.
      - Data Bus - Pins associated with data bus.
        
        Data Bus Width - Data bus width.
        
        Data Bus Pins - Data bus pins
        One item of the list looks like:
        Data Bus Pin 0 - Address bus pin.
        
        Pin - Data bus pin name (for information only).
        
        Pin signal - Pin signal user name
      - Address Bus - Pins associated with address bus.
        
        Address Bus Width - Address bus width
        One item of the list looks like:
        Address Bus Pin 0 - Address bus pin.
        
        Pin - Address bus pin name (for information only).
        
        Pin signal - Pin signal user name
      - Chip selects - Properties in this group enables one of the external chip selects CS3, CS2, CS1, and CS0 outputs which are asserted during accesses to specific external addresses. Chip selects are only active if enabled in normal expanded mode, Emulation expanded mode and special test mode. The function disabled in all other operating modes.
        
        CS0 - This property enables external chip select CS0. Global address range associated with this chip select is 0x40_0000–0x7F_FFFF. When the internal NVM is enabled (property Internal Flash) the CS0 is not asserted in the space occupied by this on-chip memory block.
        
        CS0 pin - Chip select 0 pin (for information only).
        
        CS0 pin signal - Signal name of CS0 pin.
        
        CS1 - This property enables external chip select CS1. Global address range associated with this chip select is 0x20_0000–0x3F_FFFF.
        
        CS0 pin - Chip select 1 pin (for information only).
        
        CS1 pin signal - Signal name of CS1 pin.
        
        CS2 - This property enables external chip select CS2. Global address range associated with this chip select is 0x10_0000–0x1F_FFFF.
        
        CS2 pin - Chip select 2 pin (for information only).
        
        CS2 pin signal - Signal name of CS2 pin.
        
        CS3 - This property enables external chip select CS3. Global address range associated with this chip select is 0x00_0800–0x0F_FFFF.
        
        CS3 pin - Chip select 3 pin (for information only).
        
        CS3 pin signal - Signal name of CS3 pin.
      - WE - Write Enable pin setting. (Indicates external write access, active low)
        
        WE pin - Write Enable pin (for information only).
        
        WE pin signal - Signal name of WE pin.
      - R/W - Read/Write pin setting. (Indicates the direction of internal data transfers, R - active high, W - active low)
        
        RW pin - Read/Write pin (for information only).
        
        RW pin signal - Signal name of RW pin.
      - LDS - Lower Data Select pin setting. (Indicates external access to the low byte DATA[7:0], active low)
        
        LDS pin - Lower Data Select pin (for information only).
        
        LDS pin signal - Signal name of LDS pin.
      - LSTRB - Low Strobe pin setting. (Indicates valid data on DATA[7:0], active low)
        
        LSTRB pin - Low Strobe pin (for information only).
        
        LSTRB pin signal - Signal name of LSTRB pin.
      - RE - Read Enable pin setting. (Indicates external read access)
        
        RE pin - Read Enable pin (for information only).
        
        RE pin signal - Signal name of RE pin.
      - TAGs - TAGHx pins are used to tag the high/low half of the instruction word being read into the instruction queue.
        
        TAGHI pin - TAGHI pin (for information only).
        
        TAGHI pin signal - Signal name of TAGHI pin.
        
        TAGLO pin - TAGLO pin (for information only).
        
        TAGLO pin signal - Signal name of TAGLO pin.
      - EWAIT - External control for external bus access stretches pin. (adding wait states)
        
        EWAIT pin - External control for external bus access stretches pin (for information only).
        
        EWAIT pin signal - Signal name of EWAIT pin.
      - External wait - This property enables the external access stretch function using the external EWAIT input pin. Enabling this feature may have effect on the minimum number of additional stretch cycles.
      - External Access Stretch - This property determines the amount of additional clock stretch cycles on every access to the external address space. The minimum number of stretch cycles depends on the 'External wait' property setting.
      - External memory - External memory block definitions. This list allows the user to define memories accessible on CPU external bus. Once the memory is defined, it may be used by other beans and/or compiler.
        One item of the list looks like:
        Memory block0 - External memory block
        
        Start address - Memory start address
        
        Memory size - Memory block size
        
        Memory type - Memory type: RAM or ROM
  - Emulation single-chip - See Special single-chip mode for items available in this mode.
  - Special test - See Special single-chip mode for items available in this mode.
  - Emulation expanded - See Special single-chip mode for items available in this mode.
  - Normal single-chip - See Special single-chip mode for items available in this mode.
  - Normal expanded - See Special single-chip mode for items available in this mode.
Internal peripherals - Internal peripherals setting
- BDM Debug support - If enabled then special features can be set to make debugging with BDM easier.
  - Stop COP and RTI in Active BDM mode - If this property is set to "yes" then the COP and RTI module counters are stopped in Active BDM mode.
- PWM module - PWM module settings
  - Stop in wait mode - If this property is "yes", it allows for lower power consumption in Wait Mode by disabling the input clock to the prescaler
  - Stop in freeze mode - In the Freeze Mode, there is an option to disable the input clock to the prescaler by setting this property to "yes". If this property is "yes" then whenever the MCU is in freeze mode the input clock to the prescaler is disabled.
  - Emergency shutdown - If this property is "Enabled" the pin associated with channel 7 is forced to input and the emergency shutdown feature is enabled.
    - Input active level - This property determines the active level of the PWM7 channel.
    - Shutdown output level - If active level, as defined by the previous property, gets asserted all enabled PWM channels are immediately driven to the level defined by this property.
- PIT module - PIT module settings
  - Stop in wait mode - This property is used for power conservation while in wait mode. If set to 'yes' the PIT clock generation stops and freezes the PIT module when in wait mode.
  - Stop in freeze mode - The property controls the PIT operation while in freeze mode. When during debugging a breakpoint (freeze mode) is encountered it is useful in many cases to freeze the PIT counters to avoid e.g. interrupt generation. If set to 'yes' PIT counters are stalled when in freeze mode
- ECT module - ECT module settings
  - Stop in wait mode - Disable the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait.
    Pulse accumulators and modulus down counter are also affected.
  - Stop in freeze mode - Disable the timer and modulus counter whenever the MCU is in freeze mode.
    Pulse accumulators will not stop.
  - Delay counter - If enabled, after detection of a valid edge on input capture pins, the delay counter counts the pre-selected number of bus clock cycles, then it will generate a pulse on its output. The pulse is generated only if the level of input signal, after the preset delay, is the opposite of the level before the transition.
    This property affects edge detectors on channel 0, 1, 2 and 3 (captures and pulse accumulators)
  - Mode - Input Control Latch or Queue Mode.
    Queue Mode - The main timer value is memorized in the IC register by a valid input pin transition. With a new occurrence of a capture, the value of the IC register will be transferred to its holding register (if enabled - see property Buffer) and the IC register memorizes the new timer value.
    Latch Mode - Latching function occurs when modulus down-counter reaches zero or can be invoke by SW. With a latching event the contents of IC registers and 8-bit pulse accumulators are transferred to their holding registers. 8-bit accumulators are cleared.
  - Buffer - Enable Input Capture and pulse accumulator holding registers.
    In latch mode, the holding registers are always enabled.
  - Modulus mode - If this property is "no", counter counts once from the value written to it and will stop at 0.
    In other case, when the counter reaches 0, the counter is loaded with the latest value written to the modulus count register.
  - Timer flag mode - Setting "New value in latch" allows a timer interrupt (consequently user event OnCapture) to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture.
    This property is active only in Queue mode with enabled buffers (property Mode and property Buffer).
    This property affects interrupts related with channel 0, 1, 2 and 3
  - 8-bit Pulse accumulator max. count - If this property is "yes", 8-bit pulse accumulators counters will be not incremented over value $FF (to value $00), while invoking interrupt whenever pulse appears on the input. The value $FF indicates a count of 255 or more.
  - Share input action - Share input action
    - Share capture channels 3 & 7 - If this property is "yes" then channel input 3 causes the same action on the channel 7.
    - Share capture channels 2 & 6 - If this property is "yes" then channel input 2 causes the same action on the channel 6.
    - Share capture channels 1 & 5 - If this property is "yes" then channel input 1 causes the same action on the channel 5.
    - Share capture channels 0 & 4 - If this property is "yes" then channel input 0 causes the same action on the channel 4.
- Internal Peripherals IO - Not visible
  One item of the list looks like:
  I/O module - I/O ports' settings
  - PORT A - Port A settings
    - Reduced drive for all port A - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT AD0 - Port AD0 settings
    - Reduced drive for PAD00 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD01 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD02 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD03 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD04 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD05 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD06 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD07 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT AD1H - Port AD1H settings
    - Reduced drive for PAD16 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD17 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD18 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD19 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD20 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD21 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD22 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD23 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT AD1L - Port AD1L settings
    - Reduced drive for PAD08 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD09 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD10 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD11 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD12 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD13 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD14 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PAD15 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT B - Port B settings
    - Reduced drive for all port B - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT C - Port C settings
    - Reduced drive for all port C - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT D - Port D settings
    - Reduced drive for all port D - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT E - Port E settings
    - Reduced drive for all port E - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT H - Port H settings
    - Reduced drive for PH0 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PH1 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PH2 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PH3 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PH4 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PH5 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PH6 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PH7 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT J - Port J settings
    - Reduced drive for PJ0 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PJ1 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PJ2 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PJ4 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PJ5 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PJ6 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PJ7 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT K - Port K settings
    - Reduced drive for all port K - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT M - Port M settings
    - Reduced drive for PM0 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PM1 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PM2 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PM3 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PM4 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PM5 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PM6 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PM7 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT P - Port P settings
    - Reduced drive for PP0 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PP1 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PP2 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PP3 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PP4 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PP5 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PP6 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PP7 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT S - Port S settings
    - Reduced drive for PS0 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PS1 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PS2 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PS3 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PS4 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PS5 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PS6 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PS7 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  - PORT T - Port T settings
    - Reduced drive for PT0 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PT1 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PT2 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PT3 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PT4 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PT5 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PT6 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
    - Reduced drive for PT7 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
Shared CPU interrupts - XDP512 - Shared CPU Interrupts group defined in separate file and shared among CPU beans.
One item of the list looks like:
CPU interrupts/reset - Interrupts allocated by the CPU bean.
- ClockMonitorReset - Property 'Clock monitor' in the 'Clock settings' must be set to 'Force reset' value in order to generate reset by the clock monitor.
  - Interrupt - Interrupt associated with clock monitor.
- IllegalOpcode - In order to allocate this interrupt please enable OnIllegalOpcode event.
  - Interrupt - Interrupt associated with an illegal opcode detection.
- SWI - In order to allocate this interrupt please enable OnSWI event.
  - Interrupt - Interrupt associated with the SWI.
- LVD - In order to allocate this interrupt please enable OnLvdStatusChanged event.
  - Interrupt - Interrupt associated with the LVD.
  - Interrupt priority - Interrupt priority of LVD interrupt.
- PLL - In order to allocate this interrupt please enable OnPllLockStatusChanged event. Pll must be enabled too.
  - Interrupt - Interrupt associated with the PLL.
  - Interrupt priority - Interrupt priority of PLL interrupt.
- SCM - Propery 'Clock monitor' in the 'Clock settings' must be set to 'Enter Self clock mode' value in order to generate SCM condition changed interrupt by the clock monitor.
  - Interrupt - Interrupt associated with SCM.
  - Interrupt priority - Interrupt priority of SCM interrupt.
- Spurious interrupt - In order to allocate this interrupt please enable OnSpuriousInterrupt event.
  - Interrupt - Interrupt associated with the spurious interrupt.
  - Interrupt priority - Interrupt priority of spurious interrupt.
Enabled speed modes - Enabled speed modes
- High speed mode - High speed mode support
  - Internal bus clock - Internal bus clock in high speed mode [MHz]. The Bus clock is a clock source for internal on-chip peripherals. The Core clock has the same value as the PLL clock if the PLL clock property is enabled or XTAL/2 if the PLL clock property is disabled.
  - PLL clock - PLL clock (Enabled/Disabled). The Bus clock is a clock source for internal on-chip peripherals. The Core clock has the same value as the PLL clock if the PLL clock property is enabled or XTAL/2 if the PLL clock property is disabled.
    - PLL clock frequency - PLL clock frequency [MHz]. Value of PLL clock frequency depends on bus clock frequency. This property is for information only.
    - PLL bandwidth control - Selects automatic or manual bandwidth control.
    - PLL mode - Selects acquisition or tracking mode.
  - This is a global settings specific for the CPU bean, which is not visible in this bean but may be mirrored into another beans.
    - PIT0 clock source in high speed mode - PIT0 clock source in the high speed mode.
    - PIT1 clock source in high speed mode - PIT1 clock source in the high speed mode.
    - PIT2 clock source in high speed mode - PIT2 clock source in the high speed mode.
    - PIT3 clock source in high speed mode - PIT3 clock source in the high speed mode.
    - API clock source in high speed mode - API clock source in the high speed mode.
- Low speed mode - Low speed mode support
  - Internal bus clock - Internal bus clock in low speed mode [MHz]. The Bus clock is a clock source for internal on-chip peripherals. The Core clock has the same value as the PLL clock if the PLL clock property is enabled or XTAL/2 if the PLL clock property is disabled.
  - PLL clock - PLL clock (Enabled/Disabled). The Bus clock is a clock source for internal on-chip peripherals. The Core clock has the same value as the PLL clock if the PLL clock property is enabled or XTAL/2 if the PLL clock property is disabled.
    - PLL clock frequency - PLL clock frequency [MHz]. Value of PLL clock frequency depends on bus clock frequency. This property is for information only.
    - PLL bandwidth control - Selects automatic or manual bandwidth control.
    - PLL mode - Selects acquisition or tracking mode.
  - This is a global settings specific for the CPU bean, which is not visible in this bean but may be mirrored into another beans.
    - PIT0 clock source in low speed mode - PIT0 clock source in the low speed mode.
    - PIT1 clock source in low speed mode - PIT1 clock source in the low speed mode.
    - PIT2 clock source in low speed mode - PIT2 clock source in the Low speed mode.
    - PIT3 clock source in low speed mode - PIT3 clock source in the low speed mode.
    - API clock source in low speed mode - API clock source in the low speed mode.
- Slow speed mode - Slow speed mode support
  - Internal bus clock - Internal bus clock in slow speed mode [MHz]. The Bus clock is a clock source for internal on-chip peripherals. The Core clock has the same value as the PLL clock if the PLL clock property is enabled or XTAL/2 if the PLL clock property is disabled.
  - PLL clock - PLL clock (Enabled/Disabled). The Bus clock is a clock source for internal on-chip peripherals. The Core clock has the same value as the PLL clock if the PLL clock property is enabled or XTAL/2 if the PLL clock property is disabled.
    - PLL clock frequency - PLL clock frequency [MHz]. Value of PLL clock frequency depends on bus clock frequency. This property is for information only.
    - PLL bandwidth control - Selects automatic or manual bandwidth control.
    - PLL mode - Selects acquisition or tracking mode.
  - This is a global settings specific for the CPU bean, which is not visible in this bean but may be mirrored into another beans.
    - PIT0 clock source in slow speed mode - PIT0 clock source in the slow speed mode.
    - PIT1 clock source in slow speed mode - PIT1 clock source in the slow speed mode.
    - PIT2 clock source in slow speed mode - PIT2 clock source in the slow speed mode.
    - PIT3 clock source in slow speed mode - PIT3 clock source in the slow speed mode.
    - API clock source in slow speed mode - API clock source in the slow speed mode.