MC9S12D64_112
 
General Info
Properties
Methods
Events
Used



Types & definitions
CPU Beans
Embedded Beans
Compilers
About Beans
Bean Categories



CPU Bean icon
 
  CPU Bean MC9S12D64_112
 
Freescale HC9S12 family: MC9S12D64 in 112 pinout

Parameters of the bean.

Properties:
  • Bean name - Name of the bean
  • CPU type - Cpu variant
  • Oscillator frequency [MHz] - Frequency of the main crystal or external clock. Crystal should be in range 0.5-16MHz, external clock should be in range 0.5-50MHz.
  • Initialization priority - Initialization interrupt priority value
  • Internal resource mapping - Internal resource mapping setting
  • CRG clock selection settings - This group controls the CRG module clock selection.
    • Pseudo Stop - This property controls the functionality of the oscillator during the Stop Mode.
      If this property is set to 'yes' the oscillator continues to run in the Stop Mode (Pseudo Stop). The oscillator amplitude is reduced.
      If this property is set to 'no' the oscillator is disabled in the Stop Mode.
    • System clocks stop in Wait Mode - This property controls the functionality of the oscillator during the Wait Mode.
      If this property is set to 'yes' then the system clocks are stopped in the Wait Mode.
      If this property is set to 'no' then the system clocks continue to run in the Wait Mode .
    • Reduced Oscillator Amplitude in Wait Mode - This property determines an oscillator amplitude in the Wait Mode
      If this property is set to 'yes' the oscillator amplitude will be reduced in the Wait Mode.
      If this property is set to 'no' there will be normal oscillator amplitude in the Wait Mode.
    • PLL stops in wait mode - This property determines a behavior of the PLL module in the Wait Mode
      If this property is set to 'yes' then the PLL module will operate in the Wait Mode.
      If this property is set to 'no' then the PLL module will keep running in the Wait Mode.
    • Core stops in Wait Mode - This property determines a behavior of the core clock in the Wait Mode
      If this property is set to 'yes' then the core clock stops in the Wait Mode.
      If this property is set to 'no' then the core clock keeps running in the Wait Mode.
    • RTI stops in Wait Mode - This property determines a behavior of the RTI in Wait Mode
      If this property is set to 'yes' then the RTI module is stopped and initializes the RTI dividers whenever the part goes into the Wait Mode.
      If this property is set to 'no' then the RTI module keeps running in the Wait Mode.
    • COP stops in Wait Mode - This property determines a behavior of the COP module in the Wait Mode
      If this property is set to 'yes' then the COP module is stopped and initializes the COP module dividers whenever the part goes into Wait Mode.
      If this property is set to 'no' then the COP module keeps running in the Wait Mode.
  • BDM Debug support - If enabled then special features can be set to make debugging with BDM easier.
  • Operating mode and external bus settings - CPU operating mode and external bus settings.
    • Boot operating mode - Set this property according to the CPU operating mode that is set after reset (respectively before execution of an application). This MCU mode is set by PE5/MODA, PE6/MODB and BKGD/MODC pins during reset (respectively set by debugger).
      Note:
      Processor Expert needs to known an operating mode to allocate IO pins required for selected mode and make some settings available.

      There are 8 options:
      • Special Single Chip: This mode is generally used for debugging single-chip operation, boot-strapping, or security related operations. The active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external expansion bus after reset in this mode.
      • Emulation Expanded Narrow: Developers use this mode for emulation systems in which the users target application is Normal Expanded Narrow Mode.
      • Special Test (Expanded Wide): This mode is generally used for debugging single-chip operation, boot-strapping, or security related operations. The active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external expansion bus after reset in this mode.
      • Emulation Expanded Wide: Developers use this mode for emulation systems in which the users target application is Normal Expanded Wide Mode.
      • Normal Single Chip: There is no external expansion bus in this mode. The processor program is executed from internal memory. Ports A, B, K, and most of E are available as general-purpose I/O.
      • Normal Expanded Narrow: Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with 8-bit data. Port E provides bus control and status signals. This mode allows 8-bit external memory and peripheral devices to be interfaced to the system.
      • Peripheral: This mode is intended for Motorola factory testing of the system. The CPU is inactive and an external (tester) bus master drives address, data, and bus control signals.
      • Normal Expanded Wide: Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system.

    • Operation mode switching - This property enables to generate code for switching of operating mode, i.e. it enables to change the boot operating mode by application code. This operating mode is set by 'Target operation mode' property (visible only if this property is set to 'yes')
      Set this property to 'yes' to generate code for switching of operating mode in the _EntryPoint() method.
      Note:
      Sometimes is required to boot into the some operation mode and switch to another mode by writing to the MODE register. This property allows user to switch from boot operating mode into the selected operation mode. This switching is done in the CPU _EntryPoint() function.
      If the code for switching of operating mode is undesirable, be aware that most debugging tools provide the ability to self configure the device in the debugging environment (if the part is booted into special signal-chip mode). If the CPU is to be configured for expanded operation in secure mode, the CPU must exit reset in the expanded mode. No writes to the MOD bits are allowed while operating in the secure mode. However, to release security, special single-chip mode must be possible.
      For more information see the Application note AN2287
      • Target operation mode - Set this property according to the required MCU operating mode that will be set by application code in the _EntryPoint() method.

        There are 8 options:
        • Special Single Chip: This mode is generally used for debugging single-chip operation, boot-strapping, or security related operations. The active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external expansion bus after reset in this mode.
        • Emulation Expanded Narrow: Developers use this mode for emulation systems in which the users target application is Normal Expanded Narrow Mode.
        • Special Test (Expanded Wide): This mode is generally used for debugging single-chip operation, boot-strapping, or security related operations. The active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external expansion bus after reset in this mode.
        • Emulation Expanded Wide: Developers use this mode for emulation systems in which the users target application is Normal Expanded Wide Mode.
        • Normal Single Chip: There is no external expansion bus in this mode. The processor program is executed from internal memory. Ports A, B, K, and most of E are available as general-purpose I/O.
        • Normal Expanded Narrow: Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with 8-bit data. Port E provides bus control and status signals. This mode allows 8-bit external memory and peripheral devices to be interfaced to the system.
        • Peripheral: This mode is intended for Motorola factory testing of the system. The CPU is inactive and an external (tester) bus master drives address, data, and bus control signals.
        • Normal Expanded Wide: Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system.

    • External bus settings - This group contains settings of the external bus provided by the current operation mode.
      There are 8 modes:
      • Special Single Chip - This mode is generally used for debugging single-chip operation, boot-strapping, or security related operations. The active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external expansion bus after reset in this mode. The following items are displayed in this mode:
        • Bus control signals - This property includes settings of the bus control signals.
          • External Clock - If this property is set to "Enabled" the associated pin is the external E clock pin.
            If this property is set to "Disabled" the associated pin is a general-purpose I/O pin.

            Note:
            The external clock can operate as a free-running clock at the system clock rate or to produce one low-high clock per visible access with the high period stretched for slow accesses. External clock is controlled by this property, the "Internal visibility" property, the "External clock mode" property and the "Number of E Clocks Stretched" property.
            • ECLK pin - External clock output pin (for information only).
      • Emulation Expanded Narrow - Developers use this mode for emulation systems in which the users target application is Normal Expanded Narrow Mode. The following items are displayed in this mode:
        • Internal Visibility - This property determines whether internal accesses generate a bus cycle that is visible on the external bus.
          If this property is set to "Enabled" the internal bus operations are visible on the external bus.
          If this property is set to "Disabled" there is no visibility of the internal bus operations on the external bus.
        • External paging - This property must be set to "Enable" in order to enable external paging.
          If this property is set to "Enabled" then if in any expanded mode, PORTK and DDRK are removed from the memory map and port K can be used for external paging.
          If this property is set to "Disabled" then PORTK and DDRK are in the memory map so Port K can be used for general-purpose I/O.
        • Emulate Port E - Emulate Port
          If this property is set to "Enabled" then if in any expanded mode or special peripheral mode, PORTE and DDRE are removed from the memory map. Removing the registers from the map allows the user to emulate the function of these registers externally.
          If set to "Disabled" PORTE and DDRE are in the memory map so Port E can be used for general-purpose I/O.
          In the single-chip mode, PORTE and DDRE are always in the map regardless of the state of this bit.
        • Address/Data signals - Pins associated with the external bus.
          • XABxx - Pins associated with the external bus. These output pins are enabled if the external paging is enabled (property "External paging")
            These six pins are used to determine which FLASH/ROM or external memory array page is being accessed.
            • XAB19 - XAB15 This pin is used to determine which FLASH/ROM or external memory array page is being accessed.
          • AB15-AB8,DB15-DB8 - The Port A bits 7 through 0 are associated with the address lines A15 through A8 respectively and the data lines D15/D7 respectively.
          • AB7-AB0/DB7-DB0 - The Port B bits 7 through 0 are associated with the address lines A7 through A0 respectively and the data lines D7 through D0 respectively.
        • Bus control signals - This property includes settings of the bus control signals.
          • Chip select - External chip select signals. These output pins are enabled if the external paging is enabled (property "External paging")
            • ECS - This bit is used as an emulation chip select signal for the emulation of the internal memory expansion.
            • XCS - This bit is used as an external chip select signal for most external accesses that are not selected by ECS.
          • CPU No Access Output - If this property is set to "Enabled" the associated pin is output and indicates whether the cycle is a CPU free cycle.
            If this property is set to "Disabled" the associated pin is general-purpose I/O.
            • NOACC pin - CPU No Access output. Indicates whether the current cycle is a free cycle. Only available in the expanded modes.
          • Pipe Status Signal Output - If this property is set to "Enabled" the associated pins are outputs and indicate the state of the instruction queue.
            If this property is set to "Disabled " the associated pins are general-purpose I/O.
          • External Clock - See previous modes for more details
            • ECLK pin - External clock output pin (for information only).
            • External clock mode - This property determines whether the E clock behaves as a simple free-running clock or as a bus control signal that is active only for external bus cycles.
          • Low Strobe (LSTRB) - If this property is set to "Enabled" the associated pin (Port E, bit 3) is configured as the LSTRB bus control output. If BDM tagging is enabled, TAGLO is multiplexed in on the rising edge of ECLK and LSTRB is driven out on the falling edge of ECLK.
            If this property is set to "Disabled" the associated pin (Port E, bit 3) is a general-purpose I/O pin.

            Note:
            LSTRB is used during external writes. LSTRB is disabled to provide an extra I/O pin after reset in the normal expanded mode. If LSTRB is needed it should be enabled before any external writes. External reads do not normally need LSTRB because all 16 data bits can be driven even if the system only needs 8 bits of data.
            • LSTRB pin - Low strobe bar, zero indicates valid data on D7–D0.
          • Read/Write - If this property is set to "Enabled" the associated pin (Port E, bit 2) is configured as the R/W pin.
            If this property is set to "Disabled" the associated pin (Port E, bit 2) is a general-purpose I/O pin.

            Note:
            R/W is used for external writes. R/W is disabled to provide an extra I/O pin after reset in the normal expanded mode . If R/W is needed it should be enabled before any external writes.
            • R/W pin - Read/write, indicates the direction of internal data transfers. This is an output except in special peripheral mode where it is an input.
          • External memory - External memory block definitions. This list allows the user to define memories accessible on CPU external bus. Once the memory is defined, it may be used by other beans and/or compiler.
            One item of the list looks like:
            Memory block0 - External memory block
      • Special Test (Expanded Wide) - This mode is generally used for debugging single-chip operation, boot-strapping, or security related operations. The active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external expansion bus after reset in this mode. See Emulation Expanded Narrow mode for items available in this mode.
      • Emulation Expanded Wide - Developers use this mode for emulation systems in which the users target application is Normal Expanded Wide Mode. See Emulation Expanded Narrow mode for items available in this mode.
      • Normal Single Chip - There is no external expansion bus in this mode. The processor program is executed from internal memory. Ports A, B, K, and most of E are available as general-purpose I/O. See Special Single Chip mode for items available in this mode.
      • Normal Expanded Narrow - Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with 8-bit data. Port E provides bus control and status signals. This mode allows 8-bit external memory and peripheral devices to be interfaced to the system. The following items are displayed in this mode:
        • External paging - See previous modes for more details
        • Emulate Port E - See previous modes for more details
        • Address/Data signals - Pins associated with the external bus.
          • XABxx - See previous modes for more details
            • XAB19 - See previous modes for more details
          • AB15-AB8,DB15-DB8 - See previous modes for more details
          • AB7-AB0/DB7-DB0 - See previous modes for more details
        • Bus control signals - This property includes settings of the bus control signals.
          • Chip select - See previous modes for more details
            • ECS - See previous modes for more details
            • XCS - See previous modes for more details
          • CPU No Access Output - See previous modes for more details
            • NOACC pin - See previous modes for more details
          • Pipe Status Signal Output - See previous modes for more details
          • External Clock - See previous modes for more details
            • ECLK pin - External clock output pin (for information only).
            • External clock mode - See previous modes for more details
              • Number of E Clocks Stretched - See previous modes for more details
          • Read/Write - See previous modes for more details
            • R/W pin - See previous modes for more details
          • External memory - See previous modes for more details
            One item of the list looks like:
            Memory block0 - External memory block
      • Peripheral - This mode is intended for Motorola factory testing of the system. The CPU is inactive and an external (tester) bus master drives address, data, and bus control signals. See Emulation Expanded Narrow mode for items available in this mode.
      • Normal Expanded Wide - Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system. See Emulation Expanded Narrow mode for items available in this mode.
  • Internal peripherals - Internal peripherals setting
    • PWM module - PWM module settings
      • Stop in wait mode - If this property is "yes", it allows for lower power consumption in Wait Mode by disabling the input clock to the prescaler
      • Stop in freeze mode - In Freeze Mode, there is an option to disable the input clock to the prescaler by setting this property to "yes". If this property is "yes" then whenever the MCU is in freeze mode the input clock to the prescaler is disabled.
      • Emergency shutdown - If this property is "Enabled" the pin associated with channel 7 is forced to input and the emergency shutdown feature is enabled.
        • Input active level - This property determines the active level of the PWM7 channel.
        • Shutdown output level - If active level, as defined by the previous property, gets asserted all enabled PWM channels are immediately driven to the level defined by this property.
    • ECT module - ECT module settings
      • Stop in wait mode - Disable the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait.
        Pulse accumulators and modulus down counter are also affected.
      • Stop in freeze mode - Disable the timer and modulus counter whenever the MCU is in freeze mode.
        Pulse accumulators will not stop.
      • Delay counter - If enabled, after detection of a valid edge on input capture pins, the delay counter counts the pre-selected number of bus clock cycles, then it will generate a pulse on its output. The pulse is generated only if the level of input signal, after the preset delay, is the opposite of the level before the transition.
        This property affects edge detectors on channel 0, 1, 2 and 3 (captures and pulse accumulators)
      • Mode - Input Control Latch or Queue Mode.
        Queue Mode - The main timer value is memorized in the IC register by a valid input pin transition. With a new occurrence of a capture, the value of the IC register will be transferred to its holding register (if enabled - see property Buffer) and the IC register memorizes the new timer value.
        Latch Mode - Latching function occurs when modulus down-counter reaches zero or can be invoke by SW. With a latching event the contents of IC registers and 8-bit pulse accumulators are transferred to their holding registers. 8-bit accumulators are cleared.
      • Buffer - Enable Input Capture and pulse accumulator holding registers.
        In latch mode, the holding registers are always enabled.
      • Modulus mode - If this property is "no", counter counts once from the value written to it and will stop at 0.
        In other case, when the counter reaches 0, the counter is loaded with the latest value written to the modulus count register.
      • Timer flag mode - Setting "New value in latch" allows a timer interrupt (consequently user event OnCapture) to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture.
        This property is active only in Queue mode with enabled buffers (property Mode and property Buffer).
        This property affects interrupts related with channel 0, 1, 2 and 3
      • 8-bit Pulse accumulator max. count - If this property is "yes", 8-bit pulse accumulators counters will be not incremented over value $FF (to value $00), while invoking interrupt whenever pulse appears on the input. The value $FF indicates a count of 255 or more.
      • Share input action - Share input action
    • I/O module - I/O ports' settings
      • PORT A - Port A settings
        • Reduced drive for all port A - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
      • PORT B - Port B settings
        • Reduced drive for all port B - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
      • PORT E - Port E settings
        • Reduced drive for all port E - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
      • PORT K - Port K settings
        • Reduced drive for all port K - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
      • PORT T - Port T settings
        • Reduced drive for PT0 - PT7 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
      • PORT P - Port P settings
        • Reduced drive for PP0 - PP7 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
      • PORT S - Port S settings
        • Reduced drive for PS0 - PS7 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
      • PORT M - Port M settings
        • Reduced drive for PM0 - PM7 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
      • PORT J - Port J settings
        • Reduced drive for PJ0 - PJ7 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
      • PORT H - Port H settings
        • Reduced drive for PH0 - PH7 - This property is used to select reduced drive for the pins of this port. This gives reduced power consumption and reduced RFI with slight increase in transition time.
  • CPU interrupts - Interrupts allocated by the CPU bean.
    • ClockMonitorFail - In order to allocate this interrupt please enable OnClockMonitorFail event.
      • Interrupt - Interrupt associated with clock monitor.
    • IllegalOpcode - In order to allocate this interrupt please enable OnllegalOpcode event.
      • Interrupt - Interrupt associated with an illegal opcode detection.
    • SWI - In order to allocate this interrupt please enable OnSWI event.
  • Enabled speed modes - Enabled speed modes
    • High speed mode - High speed mode support
      • Internal bus clock - Internal bus clock in high speed mode [MHz]. The Bus clock is a clock source for internal on-chip peripherals. The Core clock has the same value as the PLL clock if the PLL clock property is enabled or XTAL/2 if the PLL clock property is disabled.
      • PLL clock - PLL clock (Enabled/Disabled). The Bus clock is a clock source for internal on-chip peripherals. The Core clock has the same value as the PLL clock if the PLL clock property is enabled or XTAL/2 if the PLL clock property is disabled.
        • PLL clock frequency - PLL clock frequency [MHz]. Value of PLL clock frequency depends on bus clock frequency. This property is for information only.
        • PLL bandwidth control - Selects automatic or manual bandwidth control.
        • PLL mode - Selects acquisition or tracking mode.
    • Low speed mode - Low speed mode support
      • Internal bus clock - Internal bus clock in low speed mode [MHz]. The Bus clock is a clock source for internal on-chip peripherals. The Core clock has the same value as the PLL clock if the PLL clock property is enabled or XTAL/2 if the PLL clock property is disabled.
      • PLL clock - PLL clock (Enabled/Disabled). The Bus clock is a clock source for internal on-chip peripherals. The Core clock has the same value as the PLL clock if the PLL clock property is enabled or XTAL/2 if the PLL clock property is disabled.
        • PLL clock frequency - PLL clock frequency [MHz]. Value of PLL clock frequency depends on bus clock frequency. This property is for information only.
        • PLL bandwidth control - Selects automatic or manual bandwidth control.
        • PLL mode - Selects acquisition or tracking mode.
    • Slow speed mode - Slow speed mode support
      • Internal bus clock - Internal bus clock in slow speed mode [MHz]. The Bus clock is a clock source for internal on-chip peripherals. The Core clock has the same value as the PLL clock if the PLL clock property is enabled or XTAL/2 if the PLL clock property is disabled.
      • PLL clock - PLL clock (Enabled/Disabled). The Bus clock is a clock source for internal on-chip peripherals. The Core clock has the same value as the PLL clock if the PLL clock property is enabled or XTAL/2 if the PLL clock property is disabled.
        • PLL clock frequency - PLL clock frequency [MHz]. Value of PLL clock frequency depends on bus clock frequency. This property is for information only.
        • PLL bandwidth control - Selects automatic or manual bandwidth control.
        • PLL mode - Selects acquisition or tracking mode.


Processor ExpertTM and Embedded BeansTM are registered trademarks of UNIS, Ltd.
©1997-2005, UNIS, Ltd.