• Value registers Load Mode - This field determines the way the value registers are being loaded. This field can only be written if ENHA is set.
  This item modifies VLMODE bits in PMFCFG3 register.

  There are 3 options:
  

  • Accessed independently: Each value register is accessed independently.
  • Common writing zero to registers 0 to 5: Writing to value register zero also writes to value registers one to five.
  • Common writing one to registers 0 to 3: Writing to value register zero also writes to value registers one to three

There are 2 options:

• Independent: This bit cannot be modified after the WP bit is set.
• Complementary: This bit cannot be modified after the WP bit is set.

There are 2 options:

• Independent: This bit cannot be modified after the WP bit is set.
• Complementary: This bit cannot be modified after the WP bit is set.

There are 2 options:

• Independent: This bit cannot be modified after the WP bit is set.
• Complementary: This bit cannot be modified after the WP bit is set.

• Multiple - Multiple timebase generators. The following items are displayed in this mode:
  • PWM generator A - PWM generator A allocation.
    • Prescaler - This item selects the PWM clock frequency.
      This item modifies PRSCA bits in PMFFQCA register.

      There are 4 options:
      

      • Fbus: This is the PWM clock frequency.
      • Fbus/2: This is the PWM clock frequency.
      • Fbus/4: This is the PWM clock frequency.
      • Fbus/8: This is the PWM clock frequency.

    • Pair A Top-side PWM Polarity - This bit determines the polarity for Pair A top-side PWM (PWM0).
      This item modifies TOPNEGA bit in PMFCFG1 register.

      There are 2 options:
      

      • Negative: This bit cannot be modified after the WP bit is set.
      • Positive: This bit cannot be modified after the WP bit is set.

    • Pair A Bottom-side PWM Polarity - This bit determines the polarity for Pair A bottom-side PWM (PWM1).
      This item modifies BOTNEGA bit in PMFCFG1 register.

      There are 2 options:
      

      • Negative: This bit cannot be modified after the WP bit is set.
      • Positive: This bit cannot be modified after the WP bit is set.

    • Half Cycle Reload A - This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect on edge-aligned PWMs.
      This item modifies HALFA bit in PMFFQCA register.
    • Modulo Counter A - The 15-bit unsigned value written to this register is the PWM period in PWM clock periods.
      This item modifies 15 bits in PMFMODA register.
    • Deadtime A - The 12-bit value written to this register is the number of PWM clock cycles in complementary channel operation.
      This item modifies first 12 bits in PMFDTMA register.
    • PWM Reload Frequency A - PWM Reload Frequency A.
      This item modifies LDFQA bits in PMFFQCA register.

      There are 16 options:
      

      • Every PWM opportunity: PWM reload frequency.
      • Every 2 PWM opportunities: PWM reload frequency.
      • Every 3 PWM opportunities: PWM reload frequency.
      • Every 4 PWM opportunities: PWM reload frequency.
      • Every 5 PWM opportunities: PWM reload frequency.
      • Every 6 PWM opportunities: PWM reload frequency.
      • Every 7 PWM opportunities: PWM reload frequency.
      • Every 8 PWM opportunities: PWM reload frequency.
      • Every 9 PWM opportunities: PWM reload frequency.
      • Every 10 PWM opportunities: PWM reload frequency.
      • Every 11 PWM opportunities: PWM reload frequency.
      • Every 12 PWM opportunities: PWM reload frequency.
      • Every 13 PWM opportunities: PWM reload frequency.
      • Every 14 PWM opportunities: PWM reload frequency.
      • Every 15 PWM opportunities: PWM reload frequency.
      • Every 16 PWM opportunities: PWM reload frequency.

    • Swap Pair A - 1 = PWM0 and PWM1 are swapped only in complementary mode.
      This item modifies SWAPA bit in PMFCFG3 register.
  • PWM generator B - PWM generator B allocation.
    • Prescaler - This item selects the PWM clock frequency.
      This item modifies PRSCB bits in PMFFQCB register.

      There are 4 options:
      

      • Fbus: This is the PWM clock frequency.
      • Fbus/2: This is the PWM clock frequency.
      • Fbus/4: This is the PWM clock frequency.
      • Fbus/8: This is the PWM clock frequency.

    • Pair B Top-side PWM Polarity - This bit determines the polarity for Pair B top-side PWM (PWM2).
      This item modifies TOPNEGB bit in PMFCFG1 register.

      There are 2 options:
      

      • Negative: This bit cannot be modified after the WP bit is set.
      • Positive: This bit cannot be modified after the WP bit is set.

    • Pair B Bottom-side PWM Polarity - This bit determines the polarity for Pair B bottom-side PWM (PWM3).
      This item modifies BOTNEGB bit in PMFCFG1 register.

      There are 2 options:
      

      • Negative: This bit cannot be modified after the WP bit is set.
      • Positive: This bit cannot be modified after the WP bit is set.

    • Half Cycle Reload B - This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect on edge-aligned PWMs.
      This item modifies HALFB bit in PMFFQCB register.
    • Modulo Counter B - The 15-bit unsigned value written to this register is the PWM period in PWM clock periods.
      This item modifies 15 bits in PMFMODB register.
    • Deadtime B - The 12-bit value written to this register is the number of PWM clock cycles in complementary channel operation.
      This item modifies first 12 bits in PMFDTMB register.
    • PWM Reload Frequency B - PWM Reload Frequency B.
      This item modifies LDFQB bits in PMFFQCB register.

      There are 16 options:
      

      • Every PWM opportunity: PWM reload frequency.
      • Every 2 PWM opportunities: PWM reload frequency.
      • Every 3 PWM opportunities: PWM reload frequency.
      • Every 4 PWM opportunities: PWM reload frequency.
      • Every 5 PWM opportunities: PWM reload frequency.
      • Every 6 PWM opportunities: PWM reload frequency.
      • Every 7 PWM opportunities: PWM reload frequency.
      • Every 8 PWM opportunities: PWM reload frequency.
      • Every 9 PWM opportunities: PWM reload frequency.
      • Every 10 PWM opportunities: PWM reload frequency.
      • Every 11 PWM opportunities: PWM reload frequency.
      • Every 12 PWM opportunities: PWM reload frequency.
      • Every 13 PWM opportunities: PWM reload frequency.
      • Every 14 PWM opportunities: PWM reload frequency.
      • Every 15 PWM opportunities: PWM reload frequency.
      • Every 16 PWM opportunities: PWM reload frequency.

    • Swap Pair B - 1 = PWM4 and PWM5 are swapped only in complementary mode.
      This item modifies SWAPB bit in PMFCFG3 register.
  • PWM generator C - PWM generator C allocation.
    • Prescaler - This item selects the PWM clock frequency.
      This item modifies PRSCC bits in PMFFQCC register.

      There are 4 options:
      

      • Fbus: This is the PWM clock frequency.
      • Fbus/2: This is the PWM clock frequency.
      • Fbus/4: This is the PWM clock frequency.
      • Fbus/8: This is the PWM clock frequency.

    • Pair C Top-side PWM Polarity - This bit determines the polarity for Pair C top-side PWM (PWM4).
      This item modifies TOPNEGC bit in PMFCFG1 register.

      There are 2 options:
      

      • Negative: This bit cannot be modified after the WP bit is set.
      • Positive: This bit cannot be modified after the WP bit is set.

    • Pair C Bottom-side PWM Polarity - This bit determines the polarity for Pair C bottom-side PWM (PWM5).
      This item modifies BOTNEGC bit in PMFCFG1 register.

      There are 2 options:
      

      • Negative: This bit cannot be modified after the WP bit is set.
      • Positive: This bit cannot be modified after the WP bit is set.

    • Half Cycle Reload C - This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect on edge-aligned PWMs.
      This item modifies HALFC bit in PMFFQCC register.
    • Modulo Counter C - The 15-bit unsigned value written to this register is the PWM period in PWM clock periods.
      This item modifies 15 bits in PMFMODC register.
    • Deadtime C - The 12-bit value written to this register is the number of PWM clock cycles in complementary channel operation.
      This item modifies first 12 bits in PMFDTMC register.
    • PWM Reload Frequency C - PWM Reload Frequency C.
      This item modifies LDFQC bits in PMFFQCC register.

      There are 16 options:
      

      • Every PWM opportunity: PWM reload frequency.
      • Every 2 PWM opportunities: PWM reload frequency.
      • Every 3 PWM opportunities: PWM reload frequency.
      • Every 4 PWM opportunities: PWM reload frequency.
      • Every 5 PWM opportunities: PWM reload frequency.
      • Every 6 PWM opportunities: PWM reload frequency.
      • Every 7 PWM opportunities: PWM reload frequency.
      • Every 8 PWM opportunities: PWM reload frequency.
      • Every 9 PWM opportunities: PWM reload frequency.
      • Every 10 PWM opportunities: PWM reload frequency.
      • Every 11 PWM opportunities: PWM reload frequency.
      • Every 12 PWM opportunities: PWM reload frequency.
      • Every 13 PWM opportunities: PWM reload frequency.
      • Every 14 PWM opportunities: PWM reload frequency.
      • Every 15 PWM opportunities: PWM reload frequency.
      • Every 16 PWM opportunities: PWM reload frequency.

    • Swap Pair C - 1 = PWM4 and PWM5 are swapped only in complementary mode.
      This item modifies SWAPC bit in PMFCFG3 register.
• Single - Single timebase generator. The following items are displayed in this mode:
  • PWM generator ABC - PWM generator ABC allocation.
    • Prescaler - This item selects the PWM clock frequency.
      This item modifies PRSCA bits in PMFFQCA register.

      There are 4 options:
      

      • Fbus: This is the PWM clock frequency.
      • Fbus/2: This is the PWM clock frequency.
      • Fbus/4: This is the PWM clock frequency.
      • Fbus/8: This is the PWM clock frequency.

    • Pair A Top-side PWM Polarity - This bit determines the polarity for Pair A top-side PWM (PWM0).
      This item modifies TOPNEGA bit in PMFCFG1 register.

      There are 2 options:
      

      • Negative: This bit cannot be modified after the WP bit is set.
      • Positive: This bit cannot be modified after the WP bit is set.

    • Pair A Bottom-side PWM Polarity - This bit determines the polarity for Pair A bottom-side PWM (PWM1).
      This item modifies BOTNEGA bit in PMFCFG1 register.

      There are 2 options:
      

      • Negative: This bit cannot be modified after the WP bit is set.
      • Positive: This bit cannot be modified after the WP bit is set.

    • Pair B Top-side PWM Polarity - This bit determines the polarity for Pair B top-side PWM (PWM2).
      This item modifies TOPNEGB bit in PMFCFG1 register.

      There are 2 options:
      

      • Negative: This bit cannot be modified after the WP bit is set.
      • Positive: This bit cannot be modified after the WP bit is set.

    • Pair B Bottom-side PWM Polarity - This bit determines the polarity for Pair B bottom-side PWM (PWM3).
      This item modifies BOTNEGB bit in PMFCFG1 register.

      There are 2 options:
      

      • Negative: This bit cannot be modified after the WP bit is set.
      • Positive: This bit cannot be modified after the WP bit is set.

    • Pair C Top-side PWM Polarity - This bit determines the polarity for Pair C top-side PWM (PWM4).
      This item modifies TOPNEGC bit in PMFCFG1 register.

      There are 2 options:
      

      • Negative: This bit cannot be modified after the WP bit is set.
      • Positive: This bit cannot be modified after the WP bit is set.

    • Pair C Bottom-side PWM Polarity - This bit determines the polarity for Pair C bottom-side PWM (PWM5).
      This item modifies BOTNEGC bit in PMFCFG1 register.

      There are 2 options:
      

      • Negative: This bit cannot be modified after the WP bit is set.
      • Positive: This bit cannot be modified after the WP bit is set.

    • Half Cycle Reload - This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect on edge-aligned PWMs.
      This item modifies HALFA bit in PMFFQCA register.
    • Modulo Counter - The 15-bit unsigned value written to this register is the PWM period in PWM clock periods.
      This item modifies 15 bits in PMFMODA register.
    • Deadtime - The 12-bit value written to this register is the number of PWM clock cycles in complementary channel operation.
      This item modifies first 12 bits in PMFDTMA register.
    • PWM Reload Frequency - PWM Reload Frequency.
      This item modifies LDFQA bits in PMFFQCA register.

      There are 16 options:
      

      • Every PWM opportunity: PWM reload frequency.
      • Every 2 PWM opportunities: PWM reload frequency.
      • Every 3 PWM opportunities: PWM reload frequency.
      • Every 4 PWM opportunities: PWM reload frequency.
      • Every 5 PWM opportunities: PWM reload frequency.
      • Every 6 PWM opportunities: PWM reload frequency.
      • Every 7 PWM opportunities: PWM reload frequency.
      • Every 8 PWM opportunities: PWM reload frequency.
      • Every 9 PWM opportunities: PWM reload frequency.
      • Every 10 PWM opportunities: PWM reload frequency.
      • Every 11 PWM opportunities: PWM reload frequency.
      • Every 12 PWM opportunities: PWM reload frequency.
      • Every 13 PWM opportunities: PWM reload frequency.
      • Every 14 PWM opportunities: PWM reload frequency.
      • Every 15 PWM opportunities: PWM reload frequency.
      • Every 16 PWM opportunities: PWM reload frequency.

    • Swap Pair A - 1 = PWM0 and PWM1 are swapped only in complementary mode.
      This item modifies SWAPA bit in PMFCFG3 register.
    • Swap Pair B - 1 = PWM4 and PWM5 are swapped only in complementary mode.
      This item modifies SWAPB bit in PMFCFG3 register.
    • Swap Pair C - 1 = PWM4 and PWM5 are swapped only in complementary mode.
      This item modifies SWAPC bit in PMFCFG3 register.

• Channel 0 device - Channel 0 device selection.
• PMF Value 0 Register - The 16-bit signed value in this buffered register is the pulse width in PWM0 clock period.
  This item modifies all bits in PMFVAL0 register.
• PWM0 software control - When OUTCTL0 is set, the OUT0 bit activates and deactivates the PWM0 output.
  This item modifies OUTCTL0 bit in PMFOUTC register.
• Disable channel 0 by fault 0 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP00 bit in PMFDMPA register.
• Disable channel 0 by fault 1 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP01 bit in PMFDMPA register.
• Disable channel 0 by fault 2 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP02 bit in PMFDMPA register.
• Disable channel 0 by fault 3 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP03 bit in PMFDMPA register.
• PWM0 Mask - 1 = PWM0 is masked and the channel is set to a value of 0 percent duty cycle.
  This item modifies MSK0 bit in PMFCFG2 register.

  There are 2 options:
  

  • Masked: The channel is set to a value of 0 percent duty cycle.
  • Unmasked: PWMx is unmasked.

• Channel 1 device - Channel 1 device selection.
• PMF Value 1 Register - The 16-bit signed value in this buffered register is the pulse width in PWM1 clock period.
  This item modifies all bits in PMFVAL1 register.
• PWM1 software control - When OUTCTL1 is set, the OUT1 bit activates and deactivates the PWM1 output.
  This item modifies OUTCTL1 bit in PMFOUTC register.
• Disable channel 1 by fault 0 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP10 bit in PMFDMPA register.
• Disable channel 1 by fault 1 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP11 bit in PMFDMPA register.
• Disable channel 1 by fault 2 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP12 bit in PMFDMPA register.
• Disable channel 1 by fault 3 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP13 bit in PMFDMPA register.
• PWM1 Mask - 1 = PWM1 is masked and the channel is set to a value of 0 percent duty cycle.
  This item modifies MSK1 bit in PMFCFG2 register.

  There are 2 options:
  

  • Masked: The channel is set to a value of 0 percent duty cycle.
  • Unmasked: PWMx is unmasked.

• Channel 2 device - Channel 2 device selection.
• PWM2 software control - When OUTCTL2 is set, the OUT2 bit activates and deactivates the PWM2 output.
  This item modifies OUTCTL2 bit in PMFOUTC register.
• PMF Value 2 Register - The 16-bit signed value in this buffered register is the pulse width in PWM2 clock period.
  This item modifies all bits in PMFVAL2 register.
• Disable channel 2 by fault 0 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP20 bit in PMFDMPB register.
• Disable channel 2 by fault 1 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP21 bit in PMFDMPB register.
• Disable channel 2 by fault 2 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP22 bit in PMFDMPB register.
• Disable channel 2 by fault 3 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP23 bit in PMFDMPB register.
• PWM2 Mask - 1 = PWM2 is masked and the channel is set to a value of 0 percent duty cycle.
  This item modifies MSK2 bit in PMFCFG2 register.

  There are 2 options:
  

  • Masked: The channel is set to a value of 0 percent duty cycle.
  • Unmasked: PWMx is unmasked.

• Channel 3 device - Channel 3 device selection.
• PMF Value 3 Register - The 16-bit signed value in this buffered register is the pulse width in PWM3 clock period.
  This item modifies all bits in PMFVAL3 register.
• PWM3 software control - When OUTCTL3 is set, the OUT3 bit activates and deactivates the PWM3 output.
  This item modifies OUTCTL3 bit in PMFOUTC register.
• Disable channel 3 by fault 0 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP30 bit in PMFDMPB register.
• Disable channel 3 by fault 1 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP31 bit in PMFDMPB register.
• Disable channel 3 by fault 2 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP32 bit in PMFDMPB register.
• Disable channel 3 by fault 3 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP33 bit in PMFDMPB register.
• PWM3 Mask - 1 = PWM3 is masked and the channel is set to a value of 0 percent duty cycle.
  This item modifies MSK3 bit in PMFCFG2 register.

  There are 2 options:
  

  • Masked: The channel is set to a value of 0 percent duty cycle.
  • Unmasked: PWMx is unmasked.

• Channel 4 device - Channel 4 device selection.
• PMF Value 4 Register - The 16-bit signed value in this buffered register is the pulse width in PWM4 clock period.
  This item modifies all bits in PMFVAL4 register.
• PWM4 software control - When OUTCTL4 is set, the OUT4 bit activates and deactivates the PWM4 output.
  This item modifies OUTCTL4 bit in PMFOUTC register.
• Disable channel 4 by fault 0 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP40 bit in PMFDMPC register.
• Disable channel 4 by fault 1 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP41 bit in PMFDMPC register.
• Disable channel 4 by fault 2 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP42 bit in PMFDMPC register.
• Disable channel 4 by fault 3 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP43 bit in PMFDMPC register.
• PWM4 Mask - 1 = PWM4 is masked and the channel is set to a value of 0 percent duty cycle.
  This item modifies MSK4 bit in PMFCFG2 register.

  There are 2 options:
  

  • Masked: The channel is set to a value of 0 percent duty cycle.
  • Unmasked: PWMx is unmasked.

• Channel 5 device - Channel 5 device selection.
• PMF Value 5 Register - The 16-bit signed value in this buffered register is the pulse width in PWM5 clock period.
  This item modifies all bits in PMFVAL0 register.
• PWM5 software control - When OUTCTL5 is set, the OUT5 bit activates and deactivates the PWM5 output.
  This item modifies OUTCTL5 bit in PMFOUTC register.
• Disable channel 5 by fault 0 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP50 bit in PMFDMPC register.
• Disable channel 5 by fault 1 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP51 bit in PMFDMPC register.
• Disable channel 5 by fault 2 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP52 bit in PMFDMPC register.
• Disable channel 5 by fault 3 - The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers.
  This item modifies DMP53 bit in PMFDMPC register.
• PWM5 Mask - 1 = PWM5 is masked and the channel is set to a value of 0 percent duty cycle.
  This item modifies MSK5 bit in PMFCFG2 register.

  There are 2 options:
  

  • Masked: The channel is set to a value of 0 percent duty cycle.
  • Unmasked: PWMx is unmasked.

• Fault 0 Qualifying samples - This field indicates the number of consecutive samples taken at the FAULT0 pin to determine if a fault is detected.
  This item modifies QSMP0 bits in PMFQSMP register.

  There are 4 options:
  

  • 1: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.
  • 5: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.
  • 10: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.
  • 15: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.

• Fault 0 Pin Clearing Mode - This bit selects automatic or manual clearing of FAULT0 pin faults.
  This item modifies FMODE0 bit in PMFFCTL register.

  There are 2 options:
  

  • Automatic fault clearing: Automatic fault clearing of FAULTx pin faults.
  • Manual fault clearing: Manual fault clearing of FAULTx pin faults.

• Fault 1 Qualifying samples - This field indicates the number of consecutive samples taken at the FAULT1 pin to determine if a fault is detected.
  This item modifies QSMP1 bits in PMFQSMP register.

  There are 4 options:
  

  • 1: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.
  • 5: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.
  • 10: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.
  • 15: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.

• Fault 1 Pin Clearing Mode - This bit selects automatic or manual clearing of FAULT1 pin faults.
  This item modifies FMODE1 bit in PMFFCTL register.

  There are 2 options:
  

  • Automatic fault clearing: Automatic fault clearing of FAULTx pin faults.
  • Manual fault clearing: Manual fault clearing of FAULTx pin faults.

• Fault 2 Qualifying samples - This field indicates the number of consecutive samples taken at the FAULT2 pin to determine if a fault is detected.
  This item modifies QSMP2 bits in PMFQSMP register.

  There are 4 options:
  

  • 1: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.
  • 5: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.
  • 10: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.
  • 15: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.

• Fault 2 Pin Clearing Mode - This bit selects automatic or manual clearing of FAULT2 pin faults.
  This item modifies FMODE2 bit in PMFFCTL register.

  There are 2 options:
  

  • Automatic fault clearing: Automatic fault clearing of FAULTx pin faults.
  • Manual fault clearing: Manual fault clearing of FAULTx pin faults.

• Fault 3 Qualifying samples - This field indicates the number of consecutive samples taken at the FAULT3 pin to determine if a fault is detected.
  This item modifies QSMP3 bits in PMFQSMP register.

  There are 4 options:
  

  • 1: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.
  • 5: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.
  • 10: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.
  • 15: The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles.

• Fault 3 Pin Clearing Mode - This bit selects automatic or manual clearing of FAULT3 pin faults.
  This item modifies FMODE3 bit in PMFFCTL register.

  There are 2 options:
  

  • Automatic fault clearing: Automatic fault clearing of FAULTx pin faults.
  • Manual fault clearing: Manual fault clearing of FAULTx pin faults.

• Current status sensing method - This field selects the top/bottom correction scheme.
  This item modifies ISENS bits in PMFCCTL register.

  There are 4 options:
  

  • No correction: The ISENS bits are not buffered. Changing the current status sensing method can affect the present PWM cycle.
  • Manual correction: The ISENS bits are not buffered. Changing the current status sensing method can affect the present PWM cycle.
  • On pins IS0, IS1,IS2 during deadtime: The ISENS bits are not buffered. Changing the current status sensing method can affect the present PWM cycle.
  • On pins IS0, IS1, IS2 out of deadtime: The ISENS bits are not buffered. Changing the current status sensing method can affect the present PWM cycle.

• Current polarity for pair B - This buffered bit selects the PMF Value register for the PWM2 and PWM3 pins in top/bottom software correction in complementary mode.
  This item modifies IPOLB bit in PMFCCTL register.

  There are 2 options:
  

  • PMF Value 3 register: PMF Value 3 register in next PWM cycle.
  • PMF Value 2 register: PMF Value 2 register in next PWM cycle.

• Current polarity for pair A - This buffered bit selects the PMF Value register for the PWM0 and PWM1 pins in top/bottom software correction in complementary mode.
  This item modifies IPOLA bit in PMFCCTL register.

  There are 2 options:
  

  • PMF Value 1 register: PMF Value 1 register in next PWM cycle.
  • PMF Value 0 register: PMF Value 0 register in next PWM cycle.

• Current polarity for pair C - This buffered bit selects the PMF Value register for the PWM4 and PWM5 pins in top/bottom software correction in complementary mode.
  This item modifies IPOLC bit in PMFCCTL register.

  There are 2 options:
  

  • PMF Value 5 register: PMF Value 5 register in next PWM cycle.
  • PMF Value 4 register: PMF Value 4 register in next PWM cycle.

• PWM0 pin - For information only. Pin used for output of the generated signal.
• PWM0 pin signal - PWM0 pin signal name.

• PWM1 pin - For information only. Pin used for output of the generated signal.
• PWM1 pin signal - PWM1 pin signal name.

• PWM2 pin - For information only. Pin used for output of the generated signal.
• PWM2 pin signal - PWM2 pin signal name.

• PWM3 pin - For information only. Pin used for output of the generated signal.
• PWM3 pin signal - PWM3 pin signal name.

• PWM4 pin - For information only. Pin used for output of the generated signal.
• PWM4 pin signal - PWM4 pin signal name.

• PWM5 pin - For information only. Pin used for output of the generated signal.
• PWM5 pin signal - PWM5 pin signal name.

• Fault pin 0 - For information only. Fault pin 0.
• Fault pin 0 signal - Signal name of the fault pin 0.

• Fault pin 1 - For information only. Fault pin 1.
• Fault pin 1 signal - Signal name of the fault pin 1.

• Fault pin 2 - For information only. Fault pin 2.
• Fault pin 2 signal - Signal name of the fault pin 2.

• Fault pin 3 - For information only. Fault pin 3.
• Fault pin 3 signal - Signal name of the fault pin 3.

• Fault 0 - Fault 0 interrupt enable.
  This item modifies FIE0 bit in PMFFCTL register.
• Interrupt - Interrupt vector (for information only)
• Priority - Priority of Fault 0 interrupt.
• ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
  Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the bean module header file.

• Fault 1 - Fault 1 interrupt enable.
  This item modifies FIE1 bit in PMFFCTL register.
• Interrupt - Interrupt vector (for information only).
• Priority - Priority of Fault 1 interrupt.
• ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
  Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the bean module header file.

• Fault 2 - Fault 2 interrupt enable.
  This item modifies FIE2 bit in PMFFCTL register.
• Interrupt - Interrupt vector (for information only).
• Priority - Priority of Fault 2 interrupt.
• ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
  Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the bean module header file.

• Fault 3 - Fault 3 interrupt enable.
  This item modifies FIE3 bit in PMFFCTL register.
• Interrupt - Interrupt vector (for information only).
• Priority - Priority of Fault 3 interrupt.
• ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
  Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the bean module header file.

• Interrupt - Interrupt vector (for information only)
• Priority - Priority of PWM A Reload interrupt
• ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
  Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the bean module header file.

• Interrupt - Interrupt vector (for information only)
• Priority - Priority of PWM B Reload interrupt.
• ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
  Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the bean module header file.

• Interrupt - Interrupt vector (for information only).
• Priority - Priority of PWM C Reload interrupt.
• ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
  Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the bean module header file.